[all-commits] [llvm/llvm-project] acd6cb: [RISCV][GISel] Support fcmp and fclass for Zfh. (#...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acd6cb85b3c410e88dbcc9e48733d0e1ac70eadc
      https://github.com/llvm/llvm-project/commit/acd6cb85b3c410e88dbcc9e48733d0e1ac70eadc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-06-26 (Wed, 26 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir

  Log Message:
  -----------
  [RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)



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