[all-commits] [llvm/llvm-project] 847235: [RISCV] Add DAG combine to turn (sub (shl X, 8), X...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 847235bbef153c6d805d415cea8494297eaf2bdb
      https://github.com/llvm/llvm-project/commit/847235bbef153c6d805d415cea8494297eaf2bdb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-06-25 (Tue, 25 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to turn (sub (shl X, 8), X) into orc.b (#96680)

If only bits 8, 16, 24, 32, etc. can be non-zero.

This is what (mul X, 255) is decomposed to. This decomposition happens
early before RISC-V DAG combine runs.

This patch does not support types larger than XLen so i64 on rv32 fails
to generate 2 orc.b instructions. It might have worked if the mul hadn't
been decomposed before it was expanded.

Partial fix for #96595.



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