[all-commits] [llvm/llvm-project] a46a2c: [X86] Lower vXi8 multiplies using PMADDUBSW on SSS...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a46a2c2b7d8daf68c793b6b96f1c5bc009aea62b
      https://github.com/llvm/llvm-project/commit/a46a2c2b7d8daf68c793b6b96f1c5bc009aea62b
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-06-25 (Tue, 25 Jun 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/arith-int-codesize.ll
    M llvm/test/Analysis/CostModel/X86/arith-int-latency.ll
    M llvm/test/Analysis/CostModel/X86/arith-int-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/arith-int.ll
    M llvm/test/Analysis/CostModel/X86/rem-codesize.ll
    M llvm/test/Analysis/CostModel/X86/rem-latency.ll
    M llvm/test/Analysis/CostModel/X86/rem-sizelatency.ll
    M llvm/test/Analysis/CostModel/X86/rem.ll
    M llvm/test/Analysis/CostModel/X86/slm-arith-costs.ll
    M llvm/test/CodeGen/X86/avx2-arith.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
    M llvm/test/CodeGen/X86/min-legal-vector-width.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/prefer-avx256-wide-mul.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll

  Log Message:
  -----------
  [X86] Lower vXi8 multiplies using PMADDUBSW on SSSE3+ targets (#95690)

Extends https://github.com/llvm/llvm-project/pull/95403 to handle non-constant cases - we can avoid unpacks/extensions from vXi8 to vXi16 by using PMADDUBSW instead and truncating the vXi16 results back together.

Most targets benefit from performing this for non-constant cases - its just Intel Core/SandyBridge era CPUs that might experience additional Port0/15 contention (but lower instruction count).

Fixes https://github.com/llvm/llvm-project/issues/90748



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