[all-commits] [llvm/llvm-project] 0bd9c4: [AArch64][SVE] optimisation for SVE load intrinsic...

[Lukacma via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0bd9c49a295829ed44e838c4d54cc905662a1afa
      https://github.com/llvm/llvm-project/commit/0bd9c49a295829ed44e838c4d54cc905662a1afa
  Author: Lukacma <Marian.Lukac at arm.com>
  Date:   2024-06-25 (Tue, 25 Jun 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    A llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes-loads.ll

  Log Message:
  -----------
  [AArch64][SVE] optimisation for SVE load intrinsics with no active lanes (#95269)

This patch extends #73964 and adds optimisation of load SVE intrinsics
when predicate is zero.



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