[all-commits] [llvm/llvm-project] 2d84e0: [RISCV] Add scheduling model for Syntacore SCR3 (#...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2d84e0ffefda62da6193d339633dbb55654f7b5d
      https://github.com/llvm/llvm-project/commit/2d84e0ffefda62da6193d339633dbb55654f7b5d
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-06-25 (Tue, 25 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-ALU.s
    A llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-LSU.s

  Log Message:
  -----------
  [RISCV] Add scheduling model for Syntacore SCR3 (#95427)

Syntacore SCR3 is a microcontroller-class processor core. Overview:
https://syntacore.com/products/scr3

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>



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