[all-commits] [llvm/llvm-project] 7f1a74: [TailDup][MachineSSAUpdater] Let RewriteUse insert...

[Björn Pettersson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f1a74429dfd62a410d4b51d2e75d3677429a51a
      https://github.com/llvm/llvm-project/commit/7f1a74429dfd62a410d4b51d2e75d3677429a51a
  Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2024-06-25 (Tue, 25 Jun 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineSSAUpdater.cpp
    A llvm/test/CodeGen/AArch64/taildup-ssa-update-pr62712.mir

  Log Message:
  -----------
  [TailDup][MachineSSAUpdater] Let RewriteUse insert a COPY when needed (#95553)

When running early-tailduplication we've seen problems with machine
verifier errors due to register class mismatches after doing the machine
SSA updates.

Typical scenario is that there is a PHI node and another instruction
that is using the same vreg:

   %othervreg:otherclass = PHI %vreg:origclass, %bb
   MInstr %vreg:origclass

but then after TailDuplicator::tailDuplicateAndUpdate we get

   %othervreg:otherclass = PHI %vreg:origclass, %bb, ...
   MInstr %othervreg:otherclass

Such rewrites are only valid if 'otherclass' is equal to (or a subclass
of) 'origclass'.

The solution here is based on adding a COPY instruction to make sure we
satisfy constraints given by 'MInstr' in the example. So if 'otherclass'
isn't equal to (or a subclass of) 'origclass' we insert a copy after the
PHI like this:

   %othervreg:otherclass = PHI %vreg:origclass, %bb, ...
   %newvreg:origclass = COPY %othervreg:otherclass
   MInstr %newvreg:origclass

A special case is when it is possible to constrain the register class
instead of inserting a COPY. We currently prefer to constrain the
register class instead of inserting a COPY, even if it is a bit unclear
if that always is better (considering register pressure for the
constrained class etc.).

Fixes: https://github.com/llvm/llvm-project/issues/62712



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