[all-commits] [llvm/llvm-project] 6082a5: [RISCV] Mark all registers marked isConstant as re...

[Francis Visoiu Mistrih via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6082a50a9835907f5f90f1967e21dcd7f5ab30f1
      https://github.com/llvm/llvm-project/commit/6082a50a9835907f5f90f1967e21dcd7f5ab30f1
  Author: Francis Visoiu Mistrih <890283+francisvm at users.noreply.github.com>
  Date:   2024-06-23 (Sun, 23 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

  Log Message:
  -----------
  [RISCV] Mark all registers marked isConstant as reserved (#96002)

This makes use of the information from TableGen instead of duplicating
it in the code.



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