[all-commits] [llvm/llvm-project] d59a4c: [RISCV] Add Syntacore SCR3 processor definition (#...

[Anton Sidorenko via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d59a4cac5fe6c05da0e9088aad8f94c207423c36
      https://github.com/llvm/llvm-project/commit/d59a4cac5fe6c05da0e9088aad8f94c207423c36
  Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
  Date:   2024-06-21 (Fri, 21 Jun 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add Syntacore SCR3 processor definition (#95953)

Syntacore SCR3 is a microcontroller-class processor core. Overview:
https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

---------

Co-authored-by: Dmitrii Petrov <dmitrii.petrov at syntacore.com>



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