[all-commits] [llvm/llvm-project] 3808ba: [VPlan] Model middle block via VPIRBasicBlock. (#9...

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3808ba78dea8ef81b108862d795ff21cb463bdb1
      https://github.com/llvm/llvm-project/commit/3808ba78dea8ef81b108862d795ff21cb463bdb1
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-06-20 (Thu, 20 Jun 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlan.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/streaming-compatible-sve-no-maximize-bandwidth.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-types.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
    M llvm/test/Transforms/LoopVectorize/ARM/sphinx.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-fold-multiple-icmps.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/ordered-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
    M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
    M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
    M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
    M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
    M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
    M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll
    M llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll
    M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
    M llvm/test/Transforms/LoopVectorize/induction.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
    M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/reduction-align.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
    M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
    M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
    M llvm/test/Transforms/LoopVectorize/reduction.ll
    M llvm/test/Transforms/LoopVectorize/scalable-reduction-inloop.ll
    M llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll
    M llvm/test/Transforms/LoopVectorize/select-cmp.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll

  Log Message:
  -----------
  [VPlan] Model middle block via VPIRBasicBlock. (#95816)

Use VPIRBasicBlock to wrap the middle block and implement patching up
branches in predecessors in VPIRBasicBlock::execute. The IR middle block
is only created after skeleton creation. Initially a regular
VPBasicBlock is created, which will later be replaced by a
VPIRBasicBlock once the middle IR basic block has been created.

Note that this slightly changes the order of instructions created in the
middle block; code generated by recipe execution in the middle block
will now be inserted before the terminator (and in between the compare
to used by the terminator). The original order will be restored in
https://github.com/llvm/llvm-project/pull/92651.


PR: https://github.com/llvm/llvm-project/pull/95816



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