[all-commits] [llvm/llvm-project] 781133: [mlir][ArmSVE] Add `arm_sve.psel` operation (#95764)

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 781133037387eefa4080aa31c73554cc0452e6e6
      https://github.com/llvm/llvm-project/commit/781133037387eefa4080aa31c73554cc0452e6e6
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-06-19 (Wed, 19 Jun 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
    M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
    M mlir/test/Dialect/ArmSVE/invalid.mlir
    M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
    M mlir/test/Dialect/ArmSVE/roundtrip.mlir
    M mlir/test/Target/LLVMIR/arm-sve.mlir

  Log Message:
  -----------
  [mlir][ArmSVE] Add `arm_sve.psel` operation (#95764)

This adds a new operation for the SME/SVE2.1 psel instruction. This
allows selecting a predicate based on a bit within another predicate,
essentially allowing for 2-D predication. Informally, the semantics are:

```mlir
%pd = arm_sve.psel %p1, %p2[%index] : vector<[4]xi1>, vector<[8]xi1>
```

=>

```
if p2[index % num_elements(p2)] == 1:
  pd = p1 : type(p1)
else:
  pd = all-false : type(p1)
```



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