[all-commits] [llvm/llvm-project] 4b9112: [AMDGPU]Optimize SGPR spills (#93668)

[Vikash Gupta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b9112e88a998ce620e4683548f2afd17cc5fe95
      https://github.com/llvm/llvm-project/commit/4b9112e88a998ce620e4683548f2afd17cc5fe95
  Author: Vikash Gupta <35700483+vg0204 at users.noreply.github.com>
  Date:   2024-06-18 (Tue, 18 Jun 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

  Log Message:
  -----------
  [AMDGPU]Optimize SGPR spills (#93668)

This PR is dependent on
[#93779](https://github.com/llvm/llvm-project/pull/93779).

As currently, each SGPR Spills are lowered to go into distinct stack
slots in stack frame after SGPR allocation phase. Therefore, this patch
utilizes the capability of StackSlotColoring to ensure the stack slot
sharing if possible for stack frame index, where the SGPR spills are
occuring in the non-interfering region.

StackSlotColoring is introduced immediately after SGPR register
allocation, just to ensure that any further lowering happens on the
optimally allocated stack slots, with certain flags to indicate the
preservation of certain analysis result later to be used by RA of other
register classes.



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