[all-commits] [llvm/llvm-project] 5ac4ff: [𝘀𝗽𝗿] initial version

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscvpoc-schedule-rvv-instructions-with-same-type-first
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ac4ff3040f8a5a6cc68efffe3349ef9d181ddec
      https://github.com/llvm/llvm-project/commit/5ac4ff3040f8a5a6cc68efffe3349ef9d181ddec
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-06-18 (Tue, 18 Jun 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineScheduler.h
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/Target/RISCV/CMakeLists.txt
    A llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp
    A llvm/lib/Target/RISCV/RISCVMachineScheduler.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    A llvm/test/CodeGen/RISCV/rvv/schedule.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1



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