[all-commits] [llvm/llvm-project] fbac69: [Transforms] Replace incorrect uses of m_Deferred ...
darkbuck via All-commits
all-commits at lists.llvm.org
Mon Jun 17 09:01:02 PDT 2024
Branch: refs/heads/users/darkbuck/spr/globalisel-allow-customizing-instruction-select-pass
Home: https://github.com/llvm/llvm-project
Commit: fbac6977820a341ab3dd7e1f0a2d8881e0161c49
https://github.com/llvm/llvm-project/commit/fbac6977820a341ab3dd7e1f0a2d8881e0161c49
Author: AtariDreams <gfunni234 at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Log Message:
-----------
[Transforms] Replace incorrect uses of m_Deferred with m_Specific (#95719)
The values have been bound already, so use m_Specific.
Commit: 527e7328607ea0a55855e53a59c5030a7d07a554
https://github.com/llvm/llvm-project/commit/527e7328607ea0a55855e53a59c5030a7d07a554
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-06-16 (Sun, 16 Jun 2024)
Changed paths:
M clang/unittests/Format/ConfigParseTest.cpp
Log Message:
-----------
[clang-format][NFC] Suppress diagnostic noise in GetStyleOfFile test
Commit: 470d59d6565f564701e1a1c194aeea4903d6baa1
https://github.com/llvm/llvm-project/commit/470d59d6565f564701e1a1c194aeea4903d6baa1
Author: Shan Huang <52285902006 at stu.ecnu.edu.cn>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/dropping_debugloc_the_neg.ll
Log Message:
-----------
[DebugInfo][Reassociate] Fix missing debug location drop (#95355)
Fix #95343 .
Commit: ef18986b2033a44e69b7c3553a356e9037ac1413
https://github.com/llvm/llvm-project/commit/ef18986b2033a44e69b7c3553a356e9037ac1413
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTestVerilog.cpp
Log Message:
-----------
[clang-format] Handle Verilog delay control (#95703)
I made a mistake when I tried to make the code handle the backtick
character like the hash character. The code did not recognize the delay
control structure. It caused net names in the declaration to be aligned
to the type name instead of the first net name.
new
```Verilog
wire logic #0 mynet, //
mynet1;
```
old
```Verilog
wire logic #0 mynet, //
mynet1;
```
Commit: 15bb02650e26875c48889053d6a9697444583721
https://github.com/llvm/llvm-project/commit/15bb02650e26875c48889053d6a9697444583721
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/CodeGenCXX/modules-vtable.cppm
A clang/test/CodeGenCXX/pr70585.cppm
Log Message:
-----------
[C++20] [Modules] [Itanium ABI] Generate the vtable in the module unit of dynamic classes (#75912)
Close https://github.com/llvm/llvm-project/issues/70585 and reflect
https://github.com/itanium-cxx-abi/cxx-abi/issues/170.
The significant change of the patch is: for dynamic classes attached to
module units, we generate the vtable to the attached module units
directly and the key functions for such classes is meaningless.
Commit: e4e350e85b377e424299d26937cc60ea6868900c
https://github.com/llvm/llvm-project/commit/e4e350e85b377e424299d26937cc60ea6868900c
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M lldb/source/Interpreter/Options.cpp
Log Message:
-----------
[LLDB] Remove dead code (NFC) (#95713)
The dead code is caught by PVS studio analyzer -
https://pvs-studio.com/en/blog/posts/cpp/1126/, fragment N12.
Warning message -
V523 The 'then' statement is equivalent to the 'else' statement.
Options.cpp 1212
Commit: b7b3d1798db98c0f7071e4557e860a6fd5847602
https://github.com/llvm/llvm-project/commit/b7b3d1798db98c0f7071e4557e860a6fd5847602
Author: Poseydon42 <vvmposeydon at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/uscmp.ll
Log Message:
-----------
[InstSimplify] Implement simple folds for `ucmp`/`scmp` intrinsics (#95601)
This patch adds folds for the cases where both operands are the same or
where it can be established that the first operand is less than, equal
to, or greater than the second operand.
Commit: 1d4e857acdd93a659387b9799fa262cce2370fb0
https://github.com/llvm/llvm-project/commit/1d4e857acdd93a659387b9799fa262cce2370fb0
Author: c8ef <c8ef at outlook.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
A llvm/test/Transforms/InstCombine/avg-lsb.ll
M llvm/test/Transforms/InstCombine/lshr.ll
Log Message:
-----------
[InstCombine] simplify average of lsb (#95684)
close: #94737
alive2: https://alive2.llvm.org/ce/z/WF_7mX
In this patch, we combine `(X + Y) / 2` into `(X & Y)` only when both X
and Y are less than or equal to 1.
Commit: ede27d8d391e3917a5aa25be7903cabde4303a66
https://github.com/llvm/llvm-project/commit/ede27d8d391e3917a5aa25be7903cabde4303a66
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
Log Message:
-----------
[SimplifyCFG] Add support for sinking instructions with multiple uses (#95521)
Sinking currently only supports instructions that have zero or one uses.
Extend this to handle instructions with any number of uses, as long as
all uses are consistent (i.e. the "same" for all sinking candidates).
After #94462 this is basically just a matter of looping over all uses
instead of checking the first one only.
Commit: 5fe7f7364abcabe34f9bf157e5e6a6fa4fa0248a
https://github.com/llvm/llvm-project/commit/5fe7f7364abcabe34f9bf157e5e6a6fa4fa0248a
Author: Daniel Kiss <daniel.kiss at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
A clang/test/Driver/aarch64-fixed-register-global.c
A clang/test/Sema/aarch64-fixed-global-register.c
Log Message:
-----------
[clang][AArch64] Add validation for Global Register Variable. (#94271)
Fixes: #76426
Commit: 9b933e9c94031287d326a02276e2e09aecb17b57
https://github.com/llvm/llvm-project/commit/9b933e9c94031287d326a02276e2e09aecb17b57
Author: Ralf Jung <post at ralfj.de>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
LangRef: getelementptr: inbounds is about the object the pointer is 'based on' (#95650)
As discussed in
https://discourse.llvm.org/t/getelementptr-inbounds-inbounds-of-which-allocation/79024,
we need the pointer to be inbounds of *the* allocated object the pointer
is based on, not just any allocated object.
Commit: 5ef768d22bb33d9ab59a8ba9abe747bed9e068a2
https://github.com/llvm/llvm-project/commit/5ef768d22bb33d9ab59a8ba9abe747bed9e068a2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/include/llvm/IR/ReplaceConstant.h
M llvm/lib/IR/ReplaceConstant.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
Log Message:
-----------
[AMDGPULowerBufferFatPointers] Expand const exprs using fat pointers (#95558)
Expand all constant expressions that use fat pointers upfront, so that
the rewriting logic only has to deal with instructions and not the
constant expression variants as well.
My primary motivation is to remove the creation of illegal constant
expressions (mul and shl) from this pass, but this also cuts down quite
a bit on the amount of duplicate logic.
Commit: 525318e5dc18fb4e6ec4f4dc4c7bcf92d31aa815
https://github.com/llvm/llvm-project/commit/525318e5dc18fb4e6ec4f4dc4c7bcf92d31aa815
Author: Vikash Gupta <35700483+vg0204 at users.noreply.github.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
Log Message:
-----------
[AMDGPU][LIT] Added a MIR LIT showing the SGPR spills (#94584)
This MIR test case is added to seek the consumption of VGPR lanes being
used for SGPR spills during si-lower-sgpr-spills pass of AMDGPU pass
pipeline. Basically, in this pass, stack slots are mapped to available
VGPR lanes for spilling purpose, thus ending the need for stack slots.
In current scenario, each new SGPR spill goes into new VGPR lanes as,
being mapped from its distinct stack slots assigned during SGPR
allocation pass. It can be clearly seen in the added test case.
Commit: 94a6b9c63ec683957c1d5f520666308ac70584ec
https://github.com/llvm/llvm-project/commit/94a6b9c63ec683957c1d5f520666308ac70584ec
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Remove getOffsetOfLocalArea() (#93765)
For RISC-V, it's always 0 and I don't see any reason we will
change it in the future.
Commit: 9a86d0a6b52da4cbeb541b4631baef4ba952dfb8
https://github.com/llvm/llvm-project/commit/9a86d0a6b52da4cbeb541b4631baef4ba952dfb8
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Log Message:
-----------
[InstCombine] Prefer source over result element type (NFC)
For single-index GEPs the source and result element types are the
same, but using the source type is semantically more correct.
Commit: 995835fe6d4dd7467d8b0b1dbe6a3d9547d900c8
https://github.com/llvm/llvm-project/commit/995835fe6d4dd7467d8b0b1dbe6a3d9547d900c8
Author: Poseydon42 <vvmposeydon at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
A llvm/test/CodeGen/AArch64/scmp.ll
A llvm/test/CodeGen/AArch64/ucmp.ll
A llvm/test/CodeGen/X86/scmp.ll
A llvm/test/CodeGen/X86/ucmp.ll
Log Message:
-----------
[SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (#91871)
This PR adds initial support for the `scmp`/`ucmp` 3-way comparison
intrinsics in the SelectionDAG. Some of the expansions/lowerings
are not optimal yet.
Commit: 657ec7320d8a28171755ba0dd5afc570a5a16791
https://github.com/llvm/llvm-project/commit/657ec7320d8a28171755ba0dd5afc570a5a16791
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
M mlir/test/Target/LLVMIR/arm-sve.mlir
Log Message:
-----------
[mlir][ArmSVE] Lower predicate-sized vector.create_masks to whilelt (#95531)
This produces better/more canonical codegen than the generic LLVM
lowering, which is a pattern the backend currently does not recognize.
See: https://github.com/llvm/llvm-project/issues/81840.
Commit: 87aed824567201924d06190033843ede42b14a8d
https://github.com/llvm/llvm-project/commit/87aed824567201924d06190033843ede42b14a8d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
Log Message:
-----------
AMDGPU: Cleanup struct buffer atomic fadd intrinsic tests
Only gfx908 was tested, and the returning versions weren't tested.
Commit: e843f029b47e98ae17b9f3e72175a76653f0bd66
https://github.com/llvm/llvm-project/commit/e843f029b47e98ae17b9f3e72175a76653f0bd66
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/lib/Conversion/LLVMCommon/MemRefBuilder.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
Log Message:
-----------
mlir: fix incorrect usages of divideCeilSigned (#95680)
Follow up on #95087 to fix incorrect usage instances of
divideCeilSigned.
Commit: f838f08c8def5f49001bba9dc4f682baef04cd14
https://github.com/llvm/llvm-project/commit/f838f08c8def5f49001bba9dc4f682baef04cd14
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M lldb/include/lldb/Target/RegisterFlags.h
M lldb/source/Target/RegisterFlags.cpp
M lldb/unittests/Target/RegisterFlagsTest.cpp
Log Message:
-----------
[lldb] Add register field enum class (#90063)
This represents the enum type that can be assigned to a field using the
`<enum>` element in the target XML.
https://sourceware.org/gdb/current/onlinedocs/gdb.html/Enum-Target-Types.html
Each enumerator has:
* A non-empty name
* A value that is within the range of the field it's applied to
The XML includes a "size" but we don't need that for anything and it's a
pain to verify so I've left it out of our internal structures. When
emitting XML we'll set size to the size of the register using the enum.
An Enumerator class is added to RegisterFlags and hooked up to the
existing ToXML so lldb-server can use it to emit enums as well.
As enums are elements on the same level as flags, when emitting XML
we'll do so via the registers. Before emitting a flags element we look
at all the fields and see what enums they reference. Then print all of
those if we haven't already done so.
Functions are added to dump enum information for `register info` to use
to show the enum information.
Commit: 7e4f7fcd9c0622270269d9e01031c5059cb41dae
https://github.com/llvm/llvm-project/commit/7e4f7fcd9c0622270269d9e01031c5059cb41dae
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
A flang/test/Integration/debug-char-type-1.f90
A flang/test/Transforms/debug-char-type-1.fir
Log Message:
-----------
[flang][debug] Support fixed size character type. (#95462)
This PR adds debug support for fixed size character type. The character
type gets translated to DIStringType.
As I have noticed in comments, currently DIStringType does not have a
way to represent the underlying character type of the string. This
restricts our ability to represent wide string. As an example, this is
how the debugger shows 2 different type of string. Note that non-ascii
characters work ok with default kind string.
character(kind=4, len=5) :: str1
character(len=16) :: str2
str1 = 'hello'
str2 = 'π = 3.14'
(gdb) p str1
$1 = 'h\000\000\000e\000\000\000l\000\000\000l\000\000\000o\000\000\000'
(gdb) p str2
$2 = 'π = 3.14 '
Commit: f84056c38f1fd14881b23ace521a403e52ed7405
https://github.com/llvm/llvm-project/commit/f84056c38f1fd14881b23ace521a403e52ed7405
Author: John Brawn <john.brawn at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/Transforms/Utils/Local.cpp
A llvm/test/DebugInfo/Generic/sroa-extract-bits.ll
Log Message:
-----------
[DebugInfo] Handle DW_OP_LLVM_extract_bits in SROA (#94638)
This doesn't need any work to be done in SROA itself, but rather in
functions that it uses. Specifically:
* DIExpression::createFragmentExpression is made to understand
DW_OP_LLVM_extract_bits
* valueCoversEntireFragment is made to check the active bits instead of
the fragment size, so that it handles extract_bits correctly
Commit: 1ba8ed0cd7d03ed9b70aaf32b3d8e9205ef95ef2
https://github.com/llvm/llvm-project/commit/1ba8ed0cd7d03ed9b70aaf32b3d8e9205ef95ef2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__expected/expected.h
M libcxx/include/__locale
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__split_buffer
M libcxx/include/__utility/pair.h
M libcxx/include/array
M libcxx/include/deque
M libcxx/include/optional
M libcxx/include/tuple
M libcxx/include/variant
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
Log Message:
-----------
[libc++] Mark more types as trivially relocatable (#89724)
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: f06d96995a3e937ce125fd48efd1026256868b99
https://github.com/llvm/llvm-project/commit/f06d96995a3e937ce125fd48efd1026256868b99
Author: Paul Walker <paul.walker at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
A llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll
Log Message:
-----------
[LLVM][DAGCombiner] Extend coverage for insert_subv(undef, extract_subv(A, 0), 0) (#95242)
There is an existing combine to remove the need for extract_subv that
requires matching vector types (all fixed or all scalable).
The combine doesn't need this restriction and so I've changed it to use
ValueType's "knownBits??" interface that supports mixed vector types. In
doing so we also need extra guards to prevent invalid operations (e.g.
extracting a scalable vector from a fixed length vector).
Commit: 52d87de7a42d608ac1da33795ca0a892f2b53f36
https://github.com/llvm/llvm-project/commit/52d87de7a42d608ac1da33795ca0a892f2b53f36
Author: Andrei Safronov <safronov at espressif.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
A llvm/test/MC/Xtensa/Core/registers.s
Log Message:
-----------
[Xtensa] Fix register asm parsing. (#95551)
Fix passing temporary string object as argument to the StringRef
constructor in "parseRegister" function, because it causes errors in the
test "llvm/test/MC/Xtensa/Core/processor-control.s".
Commit: 6d973b4548e281d0b8e75e85833804bb45b6a0e8
https://github.com/llvm/llvm-project/commit/6d973b4548e281d0b8e75e85833804bb45b6a0e8
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/ABIInfoImpl.cpp
M clang/lib/CodeGen/ABIInfoImpl.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/ARC.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/CSKY.cpp
M clang/lib/CodeGen/Targets/Hexagon.cpp
M clang/lib/CodeGen/Targets/LoongArch.cpp
M clang/lib/CodeGen/Targets/MSP430.cpp
M clang/lib/CodeGen/Targets/Mips.cpp
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/PNaCl.cpp
M clang/lib/CodeGen/Targets/PPC.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/lib/CodeGen/Targets/SystemZ.cpp
M clang/lib/CodeGen/Targets/WebAssembly.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/CodeGen/Targets/XCore.cpp
M clang/test/CodeGen/X86/x86_64-vaarg.c
M clang/test/CodeGen/aarch64-varargs.c
M clang/test/CodeGen/arm-abi-vector.c
M clang/test/CodeGen/arm-vaarg.c
M clang/test/CodeGen/mips-varargs.c
M clang/test/CodeGenCXX/arm64-empty-struct.cpp
M clang/test/CodeGenCXX/x86_32-vaarg.cpp
M clang/test/CodeGenCXX/x86_64-vaarg.cpp
Log Message:
-----------
[clang][CodeGen] Return RValue from `EmitVAArg` (#94635)
This should simplify handling of resulting value by the callers.
Commit: c2d9f253e5a4074bb965e483cca2fe968b78693c
https://github.com/llvm/llvm-project/commit/c2d9f253e5a4074bb965e483cca2fe968b78693c
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/test/CodeGenCXX/init-invariant.cpp
Log Message:
-----------
[clang][CodeGen] Fix EmitInvariantStart for non-zero addrspace (#94346)
The `llvm.invariant.start` intrinsic is already overloaded to work with
memory objects in any address space. We simply instantiate the intrinsic
with the appropriate pointer type.
Fixes #94345.
Co-authored-by: Vito Kortbeek <kortbeek at synopsys.com>
Commit: 770393bb99d947b908031f83e2d064b9666740e4
https://github.com/llvm/llvm-project/commit/770393bb99d947b908031f83e2d064b9666740e4
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
Log Message:
-----------
[MachineLICM] Correctly Apply Register Masks (#95746)
Fix regression introduced in d4b8b72
Commit: 3cead572e91d3de5f8cb458f09ab39302e289d22
https://github.com/llvm/llvm-project/commit/3cead572e91d3de5f8cb458f09ab39302e289d22
Author: Corentin Ferry <corentin.ferry at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M mlir/docs/Dialects/emitc.md
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCTypes.td
A mlir/include/mlir/Dialect/EmitC/Transforms/TypeConversions.h
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/EmitC/Transforms/TypeConversions.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/invalid_types.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/EmitC/types.mlir
M mlir/test/Target/Cpp/types.mlir
Log Message:
-----------
[mlir][emitc] Add EmitC index types (#93155)
This commit adds `emitc.size_t`, `emitc.ssize_t` and `emitc.ptrdiff_t`
types to the EmitC dialect. These are used to map `index` types to C/C++
types with an explicit signedness, and are emitted in C/C++ as `size_t`,
`ssize_t` and `ptrdiff_t`.
Commit: fb59d9b9be1311ce9bb83f12bf6169378893202a
https://github.com/llvm/llvm-project/commit/fb59d9b9be1311ce9bb83f12bf6169378893202a
Author: John Brawn <john.brawn at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/test/DebugInfo/Generic/sroa-extract-bits.ll
Log Message:
-----------
[DebugInfo] Update sroa-extract-bits.ll test (#95774)
Update test due to #91724
Commit: 457e8954798b707c73ec76e0819760aaf65d0ffb
https://github.com/llvm/llvm-project/commit/457e8954798b707c73ec76e0819760aaf65d0ffb
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/RegUsageInfoCollector.cpp
Log Message:
-----------
[CodeGen] Do not include $noreg in any regmask operands. NFCI. (#95775)
Saying that a call preserves $noreg seems weird and required a
workaround in MachineLICM.
Commit: 0432221c8e6a8e5740a982076a6ae85e5ee9909e
https://github.com/llvm/llvm-project/commit/0432221c8e6a8e5740a982076a6ae85e5ee9909e
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
A flang/test/Integration/debug-allocatable-1.f90
A flang/test/Transforms/debug-allocatable-1.fir
Log Message:
-----------
[flang][debug] Support allocatables. (#95557)
This PR adds debug support for allocatable. The allocatable arrays use
the existing functionality to read the array information from
descriptor. The allocatable for the scalar shows up as pointer to the
scalar.
While testing this, I notices that values of allocated and associated
flags were swapped. This is also fixed in this PR.
Here is how the debugging of the allocatable looks like with this patch
in place.
integer, allocatable :: ar1(:, :)
real, allocatable :: sc
allocate(sc)
allocate(ar1(3, 4))
(gdb) ptype ar1
type = integer, allocatable (3,4)
(gdb) p ar1
$1 = ((5, 6, 7) (9, 10, 11) (13, 14, 15) (17, 18, 19)) (gdb) p sc
$2 = (PTR TO -> ( real )) 0x205300
(gdb) p *sc
$3 = 3.1400001
Commit: 96e8d0fd944e2732a3cf2cc125494e7235b25fa9
https://github.com/llvm/llvm-project/commit/96e8d0fd944e2732a3cf2cc125494e7235b25fa9
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Refactor creation of a shuffle mask for TBL (NFC) (#92529)
... in preparation for https://github.com/llvm/llvm-project/pull/92528
Commit: 405882db942347baf525673befe0cea0093babb6
https://github.com/llvm/llvm-project/commit/405882db942347baf525673befe0cea0093babb6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
Log Message:
-----------
AMDGPU: Fix legalization for llvm.amdgcn.struct.buffer.atomic.fadd.v2bf16
Commit: 0cfdce854d588876bfca7030be868314e84c0e5b
https://github.com/llvm/llvm-project/commit/0cfdce854d588876bfca7030be868314e84c0e5b
Author: Konstantin Varlamov <varconsteq at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M libcxx/include/vector
Log Message:
-----------
[libc++] Guard transitive include of `<locale>` with availability macro (#95686)
This is a follow-up to https://github.com/llvm/llvm-project/pull/80282.
The transitive includes of `<locale>` in `<vector>` were all guarded by
the availability macro -- the new include should also be guarded,
otherwise any users who compile with localization disabled will start
getting errors trying to include `<vector>`.
Commit: b75e7c61ffc4adea0ec5fca63ba3feba845c8303
https://github.com/llvm/llvm-project/commit/b75e7c61ffc4adea0ec5fca63ba3feba845c8303
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M flang/include/flang/Frontend/CodeGenOptions.h
M flang/include/flang/Frontend/FrontendActions.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
A flang/test/Driver/Inputs/libfun.f90
A flang/test/Driver/mlink-builtin-bc.f90
Log Message:
-----------
[flang] Add -mlink-builtin-bitcode option to fc1 (#94763)
This patch enables the -mlink-builtin-bitcode flag in fc1 so that
bitcode libraries can be linked in. This is needed for OpenMP offloading
libraries.
Commit: 7767f0d47428db66d65b07b35aa52f0507df71f9
https://github.com/llvm/llvm-project/commit/7767f0d47428db66d65b07b35aa52f0507df71f9
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/trunc.ll
Log Message:
-----------
[InstCombine] Add test for #95547 (NFC)
Commit: 534f8569a3c9fccfd5cbc5f632b63ad0cf711098
https://github.com/llvm/llvm-project/commit/534f8569a3c9fccfd5cbc5f632b63ad0cf711098
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/trunc.ll
Log Message:
-----------
[InstCombine] Don't preserve context across div
We can't preserve the context across a non-speculatable instruction,
as this might introduce a trap. Alternatively, we could also
insert all the replacement instruction at the use-site, but that
would be a more intrusive change for the sake of this edge case.
Fixes https://github.com/llvm/llvm-project/issues/95547.
Commit: 954cb5f9a220eb18afe2d0025722067a8299c41c
https://github.com/llvm/llvm-project/commit/954cb5f9a220eb18afe2d0025722067a8299c41c
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M mlir/include/mlir/Target/LLVM/ROCDL/Utils.h
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/ROCDL/Target.cpp
Log Message:
-----------
[mlir][Target] Improve ROCDL gpu serialization API (#95456)
This patch improves the ROCDL gpu serialization API by:
- Introducing the enum `AMDGCNLibraries` for specifying the AMD GCN
device code libraries to use during linking.
- Removing `getCommonBitcodeLibs` in favor of `AMDGCNLibraries`.
Previously `getCommonBitcodeLibs` would try to load all AMD GCN bitcode
librariesm now it will only load the requested libraries.
- Exposing the `compileToBinary` method and making it virtual, allowing
downstream users to re-use this method.
- Exposing `moduleToObjectImpl`, this method provides a prototype flow
for compiling to binary, allowing downstream users to re-use this
method.
- It also avoids constructing the control variables if no device
libraries are being used.
This patch also changes the behavior of the CMake flag
`DEFAULT_ROCM_PATH`. Before it would fall back to a default value of
`/opt/rocm` if not specified. However, that default value causes fragile
builds in environments with ROCm. Now, the flag falls back to the empty
string, making it clear that **the user must provide a value at LLVM
build time**.
Commit: 4bf160e3968d77334e27dc358c497703f315351f
https://github.com/llvm/llvm-project/commit/4bf160e3968d77334e27dc358c497703f315351f
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Opcodes.td
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp] Implement Complex-complex multiplication (#94891)
Share the implementation for floating-point complex-complex
multiplication with the current interpreter. This means we need a new
opcode for this, but there's no good way around that.
Commit: 57b8be463a937e5acee025f4cccdfd4ac6b73ec9
https://github.com/llvm/llvm-project/commit/57b8be463a937e5acee025f4cccdfd4ac6b73ec9
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M mlir/include/mlir/Target/LLVM/ROCDL/Utils.h
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Target/LLVM/CMakeLists.txt
M mlir/lib/Target/LLVM/ROCDL/Target.cpp
Log Message:
-----------
Revert [mlir][Target] Improve ROCDL gpu serialization API (#95790)
Reverts llvm/llvm-project#95456
Commit: a1bdb016564d3c0867e83f3bb7494bfe8128f4b6
https://github.com/llvm/llvm-project/commit/a1bdb016564d3c0867e83f3bb7494bfe8128f4b6
Author: David Green <david.green at arm.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
Log Message:
-----------
[VectorCombine] Change shuffleToIdentity to use Use. NFC
When looking up through shuffles, a Value can be multiple different leaf types
(for example an identity from one position, a splat from another). We currently
detect this by recalculating which type of leaf it is when generating, but as
more types of leafs are added (#94954) this doesn't scale very well.
This patch switches it to use Use, not Value, to more accurately detect which
type of leaf each Use should have.
Commit: 4cf1a19b7eb67f0f3e1d70b5d513b5404692119d
https://github.com/llvm/llvm-project/commit/4cf1a19b7eb67f0f3e1d70b5d513b5404692119d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
Log Message:
-----------
Reapply "AMDGPU: Handle legal v2f16/v2bf16 atomicrmw fadd for global/flat (#95394)"
This reverts commit 95b77d90aae10725ea692e120aac083ef1c1297d.
Commit: c659e3a3f8ab797e65ca72a969b74cd06b1dfbd2
https://github.com/llvm/llvm-project/commit/c659e3a3f8ab797e65ca72a969b74cd06b1dfbd2
Author: Piotr Fusik <piotr at fusion-lang.org>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[TableGen][Docs] Fix `!range` markup (#95540)
Commit: d3da134487ca62da09c51ec598798bf8eff027d3
https://github.com/llvm/llvm-project/commit/d3da134487ca62da09c51ec598798bf8eff027d3
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
Log Message:
-----------
[RISCV] Add coverage for vsetvli insertion at O0 [nfc]
In review around https://github.com/llvm/llvm-project/pull/94686, we had
a discussion about a possible O0 specific miscompile case without test
coverage. The particular case turned out not be possible to exercise in
practice, but improving our test coverage remains a good idea if we're
going to have differences in the dataflow with and without live intervals.
Commit: 62ecceba85f40d9ca886a21481bb008a78a33db8
https://github.com/llvm/llvm-project/commit/62ecceba85f40d9ca886a21481bb008a78a33db8
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-06-17 (Mon, 17 Jun 2024)
Changed paths:
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Opcodes.td
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/CodeGen/ABIInfo.cpp
M clang/lib/CodeGen/ABIInfo.h
M clang/lib/CodeGen/ABIInfoImpl.cpp
M clang/lib/CodeGen/ABIInfoImpl.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDeclCXX.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprComplex.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGVTables.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/Targets/AArch64.cpp
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/ARC.cpp
M clang/lib/CodeGen/Targets/ARM.cpp
M clang/lib/CodeGen/Targets/CSKY.cpp
M clang/lib/CodeGen/Targets/Hexagon.cpp
M clang/lib/CodeGen/Targets/LoongArch.cpp
M clang/lib/CodeGen/Targets/MSP430.cpp
M clang/lib/CodeGen/Targets/Mips.cpp
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/PNaCl.cpp
M clang/lib/CodeGen/Targets/PPC.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/lib/CodeGen/Targets/SystemZ.cpp
M clang/lib/CodeGen/Targets/WebAssembly.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/CodeGen/Targets/XCore.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/Interp/complex.cpp
M clang/test/CodeGen/X86/x86_64-vaarg.c
M clang/test/CodeGen/aarch64-varargs.c
M clang/test/CodeGen/arm-abi-vector.c
M clang/test/CodeGen/arm-vaarg.c
M clang/test/CodeGen/mips-varargs.c
M clang/test/CodeGenCXX/arm64-empty-struct.cpp
M clang/test/CodeGenCXX/init-invariant.cpp
M clang/test/CodeGenCXX/modules-vtable.cppm
A clang/test/CodeGenCXX/pr70585.cppm
M clang/test/CodeGenCXX/x86_32-vaarg.cpp
M clang/test/CodeGenCXX/x86_64-vaarg.cpp
A clang/test/Driver/aarch64-fixed-register-global.c
A clang/test/Sema/aarch64-fixed-global-register.c
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTestVerilog.cpp
M flang/include/flang/Frontend/CodeGenOptions.h
M flang/include/flang/Frontend/FrontendActions.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.h
A flang/test/Driver/Inputs/libfun.f90
A flang/test/Driver/mlink-builtin-bc.f90
A flang/test/Integration/debug-allocatable-1.f90
A flang/test/Integration/debug-char-type-1.f90
A flang/test/Transforms/debug-allocatable-1.fir
A flang/test/Transforms/debug-char-type-1.fir
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/__exception/exception_ptr.h
M libcxx/include/__expected/expected.h
M libcxx/include/__locale
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/__split_buffer
M libcxx/include/__utility/pair.h
M libcxx/include/array
M libcxx/include/deque
M libcxx/include/optional
M libcxx/include/tuple
M libcxx/include/variant
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
M libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M lldb/include/lldb/Target/RegisterFlags.h
M lldb/source/Interpreter/Options.cpp
M lldb/source/Target/RegisterFlags.cpp
M lldb/unittests/Target/RegisterFlagsTest.cpp
M llvm/docs/LangRef.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/ReplaceConstant.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/CodeGen/MachineLICM.cpp
M llvm/lib/CodeGen/RegUsageInfoCollector.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/ReplaceConstant.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/CodeGen/AArch64/scmp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
A llvm/test/CodeGen/AArch64/ucmp.ll
A llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.buffer.atomic.fadd_rtn_errors.ll
R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-constants.ll
A llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
A llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
A llvm/test/CodeGen/X86/scmp.ll
A llvm/test/CodeGen/X86/ucmp.ll
A llvm/test/DebugInfo/Generic/sroa-extract-bits.ll
A llvm/test/MC/Xtensa/Core/registers.s
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2bf16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-agent.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-v2f16-system.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll
A llvm/test/Transforms/InstCombine/avg-lsb.ll
M llvm/test/Transforms/InstCombine/lshr.ll
M llvm/test/Transforms/InstCombine/trunc.ll
M llvm/test/Transforms/InstSimplify/uscmp.ll
A llvm/test/Transforms/Reassociate/dropping_debugloc_the_neg.ll
M llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M mlir/docs/Dialects/emitc.md
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCTypes.td
A mlir/include/mlir/Dialect/EmitC/Transforms/TypeConversions.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/lib/Conversion/LLVMCommon/MemRefBuilder.cpp
M mlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/EmitC/Transforms/TypeConversions.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/invalid_types.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/EmitC/types.mlir
M mlir/test/Target/Cpp/types.mlir
M mlir/test/Target/LLVMIR/arm-sve.mlir
Log Message:
-----------
Rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/000dae270210...62ecceba85f4
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list