[all-commits] [llvm/llvm-project] f06d96: [LLVM][DAGCombiner] Extend coverage for insert_sub...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f06d96995a3e937ce125fd48efd1026256868b99
      https://github.com/llvm/llvm-project/commit/f06d96995a3e937ce125fd48efd1026256868b99
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2024-06-17 (Mon, 17 Jun 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    A llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll

  Log Message:
  -----------
  [LLVM][DAGCombiner] Extend coverage for insert_subv(undef, extract_subv(A, 0), 0) (#95242)

There is an existing combine to remove the need for extract_subv that
requires matching vector types (all fixed or all scalable).

The combine doesn't need this restriction and so I've changed it to use
ValueType's "knownBits??" interface that supports mixed vector types. In
doing so we also need extra guards to prevent invalid operations (e.g.
extracting a scalable vector from a fixed length vector).



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