[all-commits] [llvm/llvm-project] ef1898: [clang-format] Handle Verilog delay control (#95703)

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ef18986b2033a44e69b7c3553a356e9037ac1413
      https://github.com/llvm/llvm-project/commit/ef18986b2033a44e69b7c3553a356e9037ac1413
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2024-06-17 (Mon, 17 Jun 2024)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog delay control (#95703)

I made a mistake when I tried to make the code handle the backtick
character like the hash character.  The code did not recognize the delay
control structure.  It caused net names in the declaration to be aligned
to the type name instead of the first net name.

new

```Verilog
wire logic #0 mynet, //
              mynet1;
```

old

```Verilog
wire logic #0 mynet, //
     mynet1;
```



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