[all-commits] [llvm/llvm-project] 0113f2: [AArch64][SME] Enable subreg liveness tracking fo...

[Kerry McLaughlin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0113f26fad00e4798883b02eb7a049ea545a13de
      https://github.com/llvm/llvm-project/commit/0113f26fad00e4798883b02eb7a049ea545a13de
  Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
  Date:   2024-06-14 (Fri, 14 Jun 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
    M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
    M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
    M llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
    M llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
    M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
    M llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll
    M llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
    M llvm/test/CodeGen/AArch64/arm64-dup.ll
    M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
    M llvm/test/CodeGen/AArch64/arm64-ld1.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll
    M llvm/test/CodeGen/AArch64/arm64-tbl.ll
    M llvm/test/CodeGen/AArch64/arm64-zip.ll
    M llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
    M llvm/test/CodeGen/AArch64/bf16-shuffle.ll
    M llvm/test/CodeGen/AArch64/build-vector-two-dup.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
    M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
    M llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll
    M llvm/test/CodeGen/AArch64/fptoi.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/insert-subvector.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
    M llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
    M llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
    M llvm/test/CodeGen/AArch64/seqpairspill.mir
    M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
    M llvm/test/CodeGen/AArch64/shuffles.ll
    M llvm/test/CodeGen/AArch64/shufflevector.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve-merging-stores.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll
    M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
    M llvm/test/CodeGen/AArch64/tbl-loops.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
    M llvm/test/CodeGen/AArch64/vldn_shuffle.ll

  Log Message:
  -----------
   [AArch64][SME] Enable subreg liveness tracking for AArch64 (#92142)

The SME dot instructions in these tests operate on contiguous register
tuples which use one subregister from each of the loads. When using the
strided register form for all loads, enabling subreg liveness tracking
will allow us to recognise that there is no overlap between the register
tuples used by each of the dot instructions.

This is the first in a series of patches to improve the allocation of
strided and contiguous registers for SME.



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