[all-commits] [llvm/llvm-project] ab0d01: [MC] Cache MCRegAliasIterator (#93510)

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ab0d01a5f0f17f20b106b0f6cc6d1b7d13cf4d65
      https://github.com/llvm/llvm-project/commit/ab0d01a5f0f17f20b106b0f6cc6d1b7d13cf4d65
  Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
  Date:   2024-06-14 (Fri, 14 Jun 2024)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/lib/MC/MCRegisterInfo.cpp
    M llvm/test/CodeGen/ARM/constant-island-movwt.mir

  Log Message:
  -----------
  [MC] Cache MCRegAliasIterator (#93510)

AMDGPU has a lot of registers, almost 9000. Many of those registers have
aliases. For instance, SGPR0 has a ton of aliases due to the presence of
register tuples. It's even worse if you query the aliases of a register
tuple itself. A large register tuple can have hundreds of aliases
because it may include 16 registers, and each of those registers have
their own tuples as well.

The current implementation of MCRegAliasIterator is not good at this. In
some extreme cases it can iterate, 7000 more times than
necessary, just giving duplicates over and over again and using a lot of
expensive iterators.

This patch implements a cache system for MCRegAliasIterator. It does the
expensive part only once and then saves it for us so the next iterations
on that register's aliases are just a map lookup.

Furthermore, the cached data is uniqued (and sorted). Thus, this speeds
up code by both speeding up the iterator itself, but also by minimizing
the number of loop iterations users of the iterator do.



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