[all-commits] [llvm/llvm-project] 445973: [LegalizeTypes] Handle non byte-sized elt types wh...

[Björn Pettersson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 445973caceea9154b7f05a0b574ced346955be87
      https://github.com/llvm/llvm-project/commit/445973caceea9154b7f05a0b574ced346955be87
  Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2024-06-13 (Thu, 13 Jun 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
    A llvm/test/CodeGen/X86/legalize-ins-ext-vec-elt.ll

  Log Message:
  -----------
  [LegalizeTypes] Handle non byte-sized elt types when splitting INSERT/EXTRACT_VECTOR_ELT (#93357)

DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT and
DAGTypeLegalizer::SplitVecRes_EXTRACT_VECTOR_ELT did not handle
non byte-sized elements properly. In fact, it only dealt with
elements smaller than 8 bits (as well as byte-sized elements).

This patch generalizes the support for non byte-sized element by
always widening the the vector elements to next "round integer type"
(a power of 2 bit size). This should make sure that we can access a
single element via a simple byte-addressed scalar load/store.

Also removing a suspicious CustomLowerNode call from
SplitVecRes_INSERT_VECTOR_ELT. Considering that it did not reset
the Lo/Hi out arguments before the return I think that
DAGTypeLegalizer::SplitVectorResult could be fooled into registering
the input vector as being the result. This should however not have
caused any problems since DAGTypeLegalizer::SplitVectorResult is
doing the same CustomLowerNode call, making the code removed by
this patch redundant.



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