[all-commits] [llvm/llvm-project] 2fe723: [RISCV] Add Smcsrind and Sscsrind extension (#93952)

[Monad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2fe72385a4964f80e7a1c5abcd426455e4127c03
      https://github.com/llvm/llvm-project/commit/2fe72385a4964f80e7a1c5abcd426455e4127c03
  Author: Monad <yanwqmonad at gmail.com>
  Date:   2024-06-12 (Wed, 12 Jun 2024)

  Changed paths:
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/MC/RISCV/hypervisor-csr-names.s
    M llvm/test/MC/RISCV/machine-csr-names.s
    M llvm/test/MC/RISCV/supervisor-csr-names.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add Smcsrind and Sscsrind extension (#93952)

Specification link:
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc


Some CSRs (`*ireg` and `*iselect`) in Smcsrind/Sscsrind extensions are
originally defined as part of the Smaia/Ssaia extensions and are already
supported in LLVM. The missing CSRs (`*ireg2` to `*ireg6` for `m`, `s`,
and `vs`) are added in this PR.



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