[all-commits] [llvm/llvm-project] 163d03: [SPIR-V] Validate and fix bit width of scalar regi...

[Vyacheslav Levytskyy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 163d036d64609bf59183664aec244da5078dc1f1
      https://github.com/llvm/llvm-project/commit/163d036d64609bf59183664aec244da5078dc1f1
  Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
  Date:   2024-06-11 (Tue, 11 Jun 2024)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
    A llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll

  Log Message:
  -----------
  [SPIR-V] Validate and fix bit width of scalar registers (#95147)

This PR improves legalization process of SPIR-V instructions. Namely, it
introduces validation and fixing of bit width of scalar registers as a
part of pre-legalizer. A test case is added that demonstrates ability to
legalize instructions with non 8/16/32/64 bit width both with and
without vendor-specific SPIR-V extension
(SPV_INTEL_arbitrary_precision_integers). In the case of absence of the
extension, a generated SPIR-V code will fallback to 8/16/32/64 bit width
in OpTypeInt, but SPIR-V Backend still is able to legalize operations
with original integer sizes.



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