[all-commits] [llvm/llvm-project] 837dc5: [CodeGen][NewPM] Split `MachineDominatorTree` into...

[paperchalice via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 837dc542b1519df343e5a8f7b2718483530a4193
      https://github.com/llvm/llvm-project/commit/837dc542b1519df343e5a8f7b2718483530a4193
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2024-06-11 (Tue, 11 Jun 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineDominators.h
    M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    M llvm/lib/CodeGen/CodeGen.cpp
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
    M llvm/lib/CodeGen/LiveDebugVariables.cpp
    M llvm/lib/CodeGen/LiveIntervals.cpp
    M llvm/lib/CodeGen/MIRSampleProfile.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachineCSE.cpp
    M llvm/lib/CodeGen/MachineCombiner.cpp
    M llvm/lib/CodeGen/MachineDominanceFrontier.cpp
    M llvm/lib/CodeGen/MachineDominators.cpp
    M llvm/lib/CodeGen/MachineLICM.cpp
    M llvm/lib/CodeGen/MachineLoopInfo.cpp
    M llvm/lib/CodeGen/MachinePipeliner.cpp
    M llvm/lib/CodeGen/MachineRegionInfo.cpp
    M llvm/lib/CodeGen/MachineScheduler.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/PHIElimination.cpp
    M llvm/lib/CodeGen/PeepholeOptimizer.cpp
    M llvm/lib/CodeGen/PostRASchedulerList.cpp
    M llvm/lib/CodeGen/PrologEpilogInserter.cpp
    M llvm/lib/CodeGen/RegAllocBasic.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/RegAllocPBQP.cpp
    M llvm/lib/CodeGen/ShrinkWrap.cpp
    M llvm/lib/CodeGen/UnreachableBlockElim.cpp
    M llvm/lib/CodeGen/XRayInstrumentation.cpp
    M llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
    M llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
    M llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
    M llvm/lib/Target/AMDGPU/R600Packetizer.cpp
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
    M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
    M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/lib/Target/ARC/ARCBranchFinalize.cpp
    M llvm/lib/Target/ARC/ARCOptAddrMode.cpp
    M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
    M llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
    M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
    M llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
    M llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp
    M llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
    M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
    M llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
    M llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
    M llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
    M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
    M llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
    M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
    M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
    M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
    M llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
    M llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
    M llvm/lib/Target/PowerPC/PPCCTRLoopsVerify.cpp
    M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
    M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
    M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
    M llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
    M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
    M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
    M llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp

  Log Message:
  -----------
  [CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)

Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree version of `DomTreeUpdater` to
handle `SplitCriticalEdge` in some CodeGen passes.



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