[all-commits] [llvm/llvm-project] c7308d: [LSR][AArch64] Optimize chain generation based on ...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c7308d405d286674fbcd427da3f7a06f52dd70a2
      https://github.com/llvm/llvm-project/commit/c7308d405d286674fbcd427da3f7a06f52dd70a2
  Author: David Green <david.green at arm.com>
  Date:   2024-06-10 (Mon, 10 Jun 2024)

  Changed paths:
    M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
    M llvm/test/CodeGen/AArch64/sve-lsrchain.ll

  Log Message:
  -----------
  [LSR][AArch64] Optimize chain generation based on legal addressing modes (#94453)

LSR will generate chains of related instructions with a known increment
between them. With SVE, in the case of the test case, this can include
increments like 'vscale * 16 + 8'. The idea of this patch is if we have
a '+8' increment already calculated in the chain, we can generate a
(legal) '+ vscale*16' addressing mode from it, allowing us to use the
'[x16, #1, mul vl]' addressing mode instructions.

In order to do this we keep track of the known 'bases' when generating
chains in GenerateIVChain, checking for each if the accumulated
increment expression from the base neatly folds into a legal addressing
mode. If they do not we fall back to the existing LeftOverExpr, whether
it is legal or not.

This is mostly orthogonal to #88124, dealing with the generation of
chains as opposed to rest of LSR. The existing vscale addressing mode
work has greatly helped compared to the last time I looked at this,
allowing us to check that the addressing modes are indeed legal.



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