[all-commits] [llvm/llvm-project] c15b86: [clang][Interp][NFC] Add GetPtrFieldPop opcode
Fangrui Song via All-commits
all-commits at lists.llvm.org
Fri Jun 7 14:17:11 PDT 2024
Branch: refs/heads/users/MaskRay/spr/elf-implement-force-group-allocation
Home: https://github.com/llvm/llvm-project
Commit: c15b86731b78de88fadbc16ea1c2df2f60c991e9
https://github.com/llvm/llvm-project/commit/c15b86731b78de88fadbc16ea1c2df2f60c991e9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Opcodes.td
Log Message:
-----------
[clang][Interp][NFC] Add GetPtrFieldPop opcode
And change the previous GetPtrField to only peek() the base pointer.
We can get rid of a whole bunch of DupPtr ops this way.
Commit: e622996eddfb2826d258b3a3760eed195f97aabe
https://github.com/llvm/llvm-project/commit/e622996eddfb2826d258b3a3760eed195f97aabe
Author: Kristóf Umann <dkszelethus at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
A clang/lib/StaticAnalyzer/Checkers/NoOwnershipChangeVisitor.cpp
A clang/lib/StaticAnalyzer/Checkers/NoOwnershipChangeVisitor.h
Log Message:
-----------
[analyzer][NFC] Factor out NoOwnershipChangeVisitor (#94357)
In preparation for adding essentially the same visitor to StreamChecker,
this patch factors this visitor out to a common header.
I'll be the first to admit that the interface of these classes are not
terrific, but it rather tightly held back by its main technical debt,
which is NoStoreFuncVisitor, the main descendant of
NoStateChangeVisitor.
Change-Id: I99d73ccd93a18dd145bbbc83afadbb432dd42b90
Commit: be18daad06a9b431d0b4b787bba81de579e0a583
https://github.com/llvm/llvm-project/commit/be18daad06a9b431d0b4b787bba81de579e0a583
Author: Jianjian GUAN <jacquesguan at me.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/select-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
Log Message:
-----------
Reland "[RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin" (#94565)"
Commit: 8ef5c98e9f9276f09c590e22ab88a20ae86f3859
https://github.com/llvm/llvm-project/commit/8ef5c98e9f9276f09c590e22ab88a20ae86f3859
Author: uint256_t <maekawatoshiki1017 at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/docs/Benchmarking.rst
Log Message:
-----------
[docs] Fix benchmarking tips (#94724)
This PR fixes an incorrect line for setting scaling_governer in
benchmarking tips.
Commit: 36bc7410cb68e32d4416b951a118d5a799d3a226
https://github.com/llvm/llvm-project/commit/36bc7410cb68e32d4416b951a118d5a799d3a226
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
Log Message:
-----------
[test] Don't generate extra file for regalloc-amdgpu.mir test.
Commit: 1c0063b58a4fc23c94c7f5bf5a937bbdf9703cc0
https://github.com/llvm/llvm-project/commit/1c0063b58a4fc23c94c7f5bf5a937bbdf9703cc0
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/Pointer.cpp
M clang/test/AST/Interp/cxx20.cpp
Log Message:
-----------
[clang][Interp] Remove StoragKind limitation in Pointer assign operators
It's not strictly needed and did cause some test failures.
Commit: ac404632f991fc6e7dc75ef553a99676ba8002ce
https://github.com/llvm/llvm-project/commit/ac404632f991fc6e7dc75ef553a99676ba8002ce
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
Log Message:
-----------
[NFC][LoongArch] Update test for #94590
Commit: 4f320e6aa2d4fdcb3d749977c840cdf1783173f3
https://github.com/llvm/llvm-project/commit/4f320e6aa2d4fdcb3d749977c840cdf1783173f3
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.h
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/test/CAPI/llvm.c
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
Log Message:
-----------
[MLIR] Translate DIStringType. (#94480)
This PR handle translation of DIStringType. Mostly mechanical changes to
translate DIStringType to/from DIStringTypeAttr. The 'stringLength'
field is 'DIVariable' in DIStringType. As there was no `DIVariableAttr`
previously, it has been added to ease the translation.
---------
Co-authored-by: Tobias Gysi <tobias.gysi at nextsilicon.com>
Commit: 5f1adf0433c6007f8be885b832c852da67e8524c
https://github.com/llvm/llvm-project/commit/5f1adf0433c6007f8be885b832c852da67e8524c
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang-tools-extra/clangd/FindSymbols.cpp
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/refactor/Rename.cpp
M clang-tools-extra/clangd/unittests/PreambleTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/include/clang/Tooling/Syntax/Tokens.h
M clang/lib/Tooling/Syntax/Tokens.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
Log Message:
-----------
[clangd] Fix crash with null check for Token at Loc (#94528)
Fixes https://github.com/llvm/llvm-project/issues/94599
Commit: 8f1164948d6b8f3d3ea11d0ee0629af82fe8cb74
https://github.com/llvm/llvm-project/commit/8f1164948d6b8f3d3ea11d0ee0629af82fe8cb74
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Optimizer/Transforms/VScaleAttr.cpp
Log Message:
-----------
[flang][Transforms][NFC] Remove boilerplate from vscale range pass (#94598)
Use tablegen to generate the pass constructor.
This pass is supposed to add function attributes so it does not need to
operate on other top level operations.
Commit: 0749b01c81b7397f674cfe3726e13aa9dfb702ea
https://github.com/llvm/llvm-project/commit/0749b01c81b7397f674cfe3726e13aa9dfb702ea
Author: Chen Zheng <czhengsz at cn.ibm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/CodeGen/PowerPC/frameaddr.ll
Log Message:
-----------
[PowerPC] modify the frameaddress case, NFC
Commit: 3453dedfaf565429bc06c6d58533926f793ad650
https://github.com/llvm/llvm-project/commit/3453dedfaf565429bc06c6d58533926f793ad650
Author: Chen Zheng <czhengsz at cn.ibm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
M llvm/test/CodeGen/PowerPC/frameaddr.ll
Log Message:
-----------
[PowerPC] return correct frame address for frameaddress intrinsic
Commit: c0b468523c9c5517e61a197e7c1fe6cb52f8999c
https://github.com/llvm/llvm-project/commit/c0b468523c9c5517e61a197e7c1fe6cb52f8999c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/test/CodeGen/ARM/neon_vabd.ll
Log Message:
-----------
[ARM] Add NEON support for ISD::ABDS/ABDU nodes. (#94504)
As noted on #94466, NEON has ABDS/ABDU instructions but only handles them via intrinsics, plus some VABDL custom patterns.
This patch flags basic ABDS/ABDU for neon types as legal and updates all tablegen patterns to use abds/abdu instead.
Fixes #94466
Commit: 0d1b3671a91c3929fc3e3613491ff4b57f1adcc3
https://github.com/llvm/llvm-project/commit/0d1b3671a91c3929fc3e3613491ff4b57f1adcc3
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M .github/workflows/release-binaries.yml
M clang/cmake/caches/Release.cmake
Log Message:
-----------
[CMake][Release] Use the TXZ cpack generator for binaries (#90138)
Commit: 1721c14e8e0d75cc611067b6f4e84028ea7c47d5
https://github.com/llvm/llvm-project/commit/1721c14e8e0d75cc611067b6f4e84028ea7c47d5
Author: John Brawn <john.brawn at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
A llvm/test/DebugInfo/X86/DW_OP_LLVM_extract_bits.ll
Log Message:
-----------
[DebugInfo] Add DW_OP_LLVM_extract_bits (#93990)
This operation extracts a number of bits at a given offset and sign or
zero extends them, which is done by emitting it as a left shift followed
by a right shift.
This is being added for use in clang for C++ structured bindings of
bitfields that have offset or size that aren't a byte multiple. A new
operation is being added, instead of shifts being used directly, as it
makes correctly handling it in optimisations (which will be done in a
later patch) much easier.
Commit: 192cd685129d6f42e8b191e12bddf74ade48c270
https://github.com/llvm/llvm-project/commit/192cd685129d6f42e8b191e12bddf74ade48c270
Author: Fotis Kounelis <fotisss17 at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/test/Dialect/SCF/transform-ops.mlir
Log Message:
-----------
Add checks before hoisting out in loop pipelining (#90872)
Currently, during a loop pipelining transformation, operations may be
hoisted out without any checks on the loop bounds, which leads to
incorrect transformations and unexpected behaviour. The following [issue
](https://github.com/llvm/llvm-project/issues/90870) describes the
problem more extensively, including an example.
The proposed fix adds some check in the loop bounds before and applies
the maximum hoisting.
Commit: 5d6acf8196a44225991ab2fb6dfc9cc72296b348
https://github.com/llvm/llvm-project/commit/5d6acf8196a44225991ab2fb6dfc9cc72296b348
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/Pointer.cpp
Log Message:
-----------
[clang][Interp][NFC] Properly assign block pointer Pointee
Commit: 3a31eaeac8482fa5e242ee00cd4e77b203db539e
https://github.com/llvm/llvm-project/commit/3a31eaeac8482fa5e242ee00cd4e77b203db539e
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/lambda.cpp
Log Message:
-----------
[clang][Interp] Fix refers_to_enclosing_variable_or_capture DREs
They do not count into lambda captures, so visit them lazily.
Commit: 1934c1aa3613fe2ded87ca4cd739694378e92601
https://github.com/llvm/llvm-project/commit/1934c1aa3613fe2ded87ca4cd739694378e92601
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/Transforms/SimplifyCFG/ARM/switch-to-lookup-table.ll
Log Message:
-----------
[SimplifyCFG] Remove bogus UTC line from test (NFC)
The check lines in this test were clearly not generated by UTC.
Commit: 8719cb88e3443bf717391b5020beab61238a372c
https://github.com/llvm/llvm-project/commit/8719cb88e3443bf717391b5020beab61238a372c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll
M llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
Log Message:
-----------
[SimplifyCFG] Regenerate switch to lookup tests (NFC)
Regenerate these with --check-globals. The manual global CHECKS
get dropped during regeneration otherwise.
Annoyingly UTC insists on putting the globals directly before the
first function, so the first comment is a bit out of place now.
Commit: b87a80d4ebca9e1c065f0d2762e500078c4badca
https://github.com/llvm/llvm-project/commit/b87a80d4ebca9e1c065f0d2762e500078c4badca
Author: Mubashar Ahmad <mubashar.ahmad at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
A mlir/test/Dialect/Vector/vector-deinterleave-lowering-transforms.mlir
Log Message:
-----------
[mlir][vector] Add n-d deinterleave lowering (#94237)
This patch implements the lowering for vector
deinterleave for vector of n-dimensions. Process
involves unrolling the n-d vector to a series
of one-dimensional vectors. The deinterleave
operation is then used on these vectors.
From:
```
%0, %1 = vector.deinterleave %a : vector<2x8xi8> -> vector<2x4xi8>
```
To:
```
%cst = arith.constant dense<0> : vector<2x4xi32>
%0 = vector.extract %arg0[0] : vector<8xi32> from vector<2x8xi32>
%res1, %res2 = vector.deinterleave %0 : vector<8xi32> -> vector<4xi32>
%1 = vector.insert %res1, %cst [0] : vector<4xi32> into vector<2x4xi32>
%2 = vector.insert %res2, %cst [0] : vector<4xi32> into vector<2x4xi32>
%3 = vector.extract %arg0[1] : vector<8xi32> from vector<2x8xi32>
%res1_0, %res2_1 = vector.deinterleave %3 : vector<8xi32> -> vector<4xi32>
%4 = vector.insert %res1_0, %1 [1] : vector<4xi32> into vector<2x4xi32>
%5 = vector.insert %res2_1, %2 [1] : vector<4xi32> into vector<2x4xi32>
...etc.
```
Commit: 1a5239251ead73ee57f4e2f7fc93433ac7cf18b1
https://github.com/llvm/llvm-project/commit/1a5239251ead73ee57f4e2f7fc93433ac7cf18b1
Author: Oliver Stannard <oliver.stannard at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M llvm/docs/LangRef.rst
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/TargetOptionsImpl.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
M llvm/test/CodeGen/ARM/frame-chain.ll
M llvm/test/CodeGen/Thumb/frame-access.ll
M llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
M llvm/test/CodeGen/Thumb/frame-chain.ll
Log Message:
-----------
[ARM] r11 is reserved when using -mframe-chain=aapcs (#86951)
When using the -mframe-chain=aapcs or -mframe-chain=aapcs-leaf options,
we cannot use r11 as an allocatable register, even if
-fomit-frame-pointer is also used. This is so that r11 will always point
to a valid frame record, even if we don't create one in every function.
Commit: af3ffff34fb39cfb1e19dce68bd1c3fefda336a4
https://github.com/llvm/llvm-project/commit/af3ffff34fb39cfb1e19dce68bd1c3fefda336a4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/pr38539.ll
Log Message:
-----------
[DAG] Always allow folding XOR patterns to ABS pre-legalization (#94601)
Removes residual ARM handling for vXi64 ABS nodes to prevent infinite loops.
Commit: fd45dcca26d6031fcbaa907d8d6c0d9755b36699
https://github.com/llvm/llvm-project/commit/fd45dcca26d6031fcbaa907d8d6c0d9755b36699
Author: Eisuke Kawashima <e.kawaschima+github at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/test/python/ir/affine_expr.py
M mlir/test/python/ir/attributes.py
M mlir/test/python/ir/builtin_types.py
Log Message:
-----------
fix(mlir/**.py): fix comparison to None (#94019)
from PEP8
(https://peps.python.org/pep-0008/#programming-recommendations):
> Comparisons to singletons like None should always be done with is or
is not, never the equality operators.
Co-authored-by: Eisuke Kawashima <e-kwsm at users.noreply.github.com>
Commit: 917afa883258757575ac6448e83a9233d7877333
https://github.com/llvm/llvm-project/commit/917afa883258757575ac6448e83a9233d7877333
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/test/Misc/target-invalid-cpu-note.c
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/TargetParser/ARMTargetParser.def
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/test/CodeGen/ARM/build-attributes.ll
M llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll
M llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
M llvm/test/CodeGen/ARM/misched-fp-basic.ll
M llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
M llvm/test/CodeGen/ARM/misched-int-basic.mir
M llvm/test/CodeGen/ARM/proc-resource-sched.ll
M llvm/test/CodeGen/ARM/single-issue-r52.mir
M llvm/test/CodeGen/ARM/useaa.ll
M llvm/test/MC/ARM/dfb-neg.s
M llvm/test/MC/ARM/dfb.s
A llvm/test/MC/ARM/invalid-armv8r.s
M llvm/test/MC/ARM/thumb-hints.s
M llvm/test/MC/Disassembler/ARM/dfb-thumb.txt
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[ARM] Add support for Cortex-R52+ (#94633)
Cortex-R52+ is an Armv8-R AArch32 CPU.
Technical Reference Manual for Cortex-R52+:
https://developer.arm.com/documentation/102199/latest/
Commit: 537165bb02df8e9f4dc4c21725d50e77e2908a5f
https://github.com/llvm/llvm-project/commit/537165bb02df8e9f4dc4c21725d50e77e2908a5f
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
Log Message:
-----------
[NFC][LoongArch] Update test for #94590
Commit: 54c5dbe7c3812461decbccb6ed122e41777e02bd
https://github.com/llvm/llvm-project/commit/54c5dbe7c3812461decbccb6ed122e41777e02bd
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/unittests/Interpreter/InterpreterTest.cpp
Log Message:
-----------
[clang][test] Skip interpreter value test on Arm 32 bit
https://github.com/llvm/llvm-project/pull/89811 caused this test to fail,
somehow.
I think it may not be at fault, but actually be exposing some
existing undefined behaviour, see
https://github.com/llvm/llvm-project/issues/94741.
Skipping this for now to get the bots green again.
Commit: d3e531cf37ed5334aa873e4e46aff693efac9d77
https://github.com/llvm/llvm-project/commit/d3e531cf37ed5334aa873e4e46aff693efac9d77
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
Log Message:
-----------
[gn build] Port e622996eddfb
Commit: 6fe5428ecbd18aa263417a244c0850b1271617c0
https://github.com/llvm/llvm-project/commit/6fe5428ecbd18aa263417a244c0850b1271617c0
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Flang.cpp
Log Message:
-----------
[Flang] Handle the newly-added "Reserved" FramePointerKind for 1a5239251ead73ee57f4e2f7fc93433ac7cf18b1
Commit: 88e2bb40921f35663e16e45514de20018615c36f
https://github.com/llvm/llvm-project/commit/88e2bb40921f35663e16e45514de20018615c36f
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/target-data.c
A clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
A clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
M clang/test/CodeGenCUDA/long-double.cu
A clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
A clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
M clang/test/CodeGenHIP/hipspv-addr-spaces.cpp
A clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
A clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
A clang/test/CodeGenHIP/spirv-amdgcn-half.hip
M clang/test/CodeGenOpenCL/amdgcn-flat-scratch-name.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl
M clang/test/Preprocessor/hash_builtin.cpp
M clang/test/Preprocessor/predefined-macros-no-warnings.c
M clang/test/Preprocessor/predefined-macros.c
A clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
A clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
M clang/test/SemaCUDA/allow-int128.cu
M clang/test/SemaCUDA/amdgpu-f128.cu
M clang/test/SemaCUDA/float16.cu
M clang/test/SemaCUDA/fp16-arg-return.cu
A clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx940-param.cl
M llvm/docs/SPIRVUsage.rst
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll
M llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll
Log Message:
-----------
[clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (#89796)
This change seeks to add support for vendor flavoured SPIRV - more
specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV that
carries some extra bits of information that are only usable by AMDGCN
targets, forfeiting absolute genericity to obtain greater expressiveness
for target features:
- AMDGCN inline ASM is allowed/supported, under the assumption that the
[SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc)
extension is enabled/used
- AMDGCN target specific builtins are allowed/supported, under the
assumption that e.g. the `--spirv-allow-unknown-intrinsics` option is
enabled when using the downstream translator
- the featureset matches the union of AMDGCN targets' features
- the datalayout string is overspecified to affix both the program
address space and the alloca address space, the latter under the
assumption that the
[SPV_INTEL_function_pointers](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc)
extension is enabled/used, case in which the extant SPIRV datalayout
string would lead to pointers to function pointing to the private
address space, which would be wrong.
Existing AMDGCN tests are extended to cover this new target. It is
currently dormant / will require some additional changes, but I thought
I'd rather put it up for review to get feedback as early as possible. I
will note that an alternative option is to place this under AMDGPU, but
that seems slightly less natural, since this is still SPIRV, albeit
relaxed in terms of preconditions & constrained in terms of
postconditions, and only guaranteed to be usable on AMDGCN targets (it
is still possible to obtain pristine portable SPIRV through usage of the
flavoured target, though).
Commit: 3fefb3c598db995433093ed158c08368809b3f78
https://github.com/llvm/llvm-project/commit/3fefb3c598db995433093ed158c08368809b3f78
Author: Nathan Sidwell <nathan at acm.org>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/VeneerElimination.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][NFC] Infailable fns return void (#92018)
Both `reverseBranchCondition` and `replaceBranchTarget` return a success boolean. But all-but-one caller ignores the return value, and the exception emits a fatal error on failure.
Thus, just return nothing.
Commit: 74d62c2f73799ea6ffbf165ff752ca0b0f826eca
https://github.com/llvm/llvm-project/commit/74d62c2f73799ea6ffbf165ff752ca0b0f826eca
Author: aengelke <engelke at in.tum.de>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[CodeGen][SDAG] Remove CombinedNodes SmallPtrSet (#94609)
This "small" set grows quite large and it's more performant to store
whether a node has been combined before in the node itself.
As this information is only relevant for nodes that are currently not in
the worklist, add a second state to the CombinerWorklistIndex (-2) to
indicate that a node is currently not in a worklist, but was combined
before.
This brings a substantial performance improvement.
Commit: 9ece3eb1459309f9fbd18ce8ec8f771c238e8815
https://github.com/llvm/llvm-project/commit/9ece3eb1459309f9fbd18ce8ec8f771c238e8815
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/EvalEmitter.cpp
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/test/AST/Interp/cxx20.cpp
Log Message:
-----------
[clang][Interp] Check ConstantExpr results for initialization
They need to be fully initialized, similar to global variables.
Commit: 9eb8a130c5d708dbabe824113add072436ae9997
https://github.com/llvm/llvm-project/commit/9eb8a130c5d708dbabe824113add072436ae9997
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/MemberPointer.h
Log Message:
-----------
[clang][Interp][NFC] Fix a const-correctness warning
Commit: b8cc85b318c0dd89e4dd69e3691ffcad5e401885
https://github.com/llvm/llvm-project/commit/b8cc85b318c0dd89e4dd69e3691ffcad5e401885
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/lambda.cpp
Log Message:
-----------
[clang][Interp] Limit lambda capture lazy visting to actual captures
Check this by looking at the VarDecl.
Commit: 5a0181f568e56e37df80d0f74eca4775776fa8cd
https://github.com/llvm/llvm-project/commit/5a0181f568e56e37df80d0f74eca4775776fa8cd
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/AST/ASTUnresolvedSet.h
M clang/include/clang/AST/DeclAccessPair.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclID.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/Serialization/ModuleManager.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ModuleFile.cpp
A clang/test/Modules/no-transitive-decls-change.cppm
Log Message:
-----------
[serialization] no transitive decl change (#92083)
Following of https://github.com/llvm/llvm-project/pull/86912
The motivation of the patch series is that, for a module interface unit
`X`, when the dependent modules of `X` changes, if the changes is not
relevant with `X`, we hope the BMI of `X` won't change. For the specific
patch, we hope if the changes was about irrelevant declaration changes,
we hope the BMI of `X` won't change. **However**, I found the patch
itself is not very useful in practice, since the adding or removing
declarations, will change the state of identifiers and types in most
cases.
That said, for the most simple example,
```
// partA.cppm
export module m:partA;
// partA.v1.cppm
export module m:partA;
export void a() {}
// partB.cppm
export module m:partB;
export void b() {}
// m.cppm
export module m;
export import :partA;
export import :partB;
// onlyUseB;
export module onlyUseB;
import m;
export inline void onluUseB() {
b();
}
```
the BMI of `onlyUseB` will change after we change the implementation of
`partA.cppm` to `partA.v1.cppm`. Since `partA.v1.cppm` introduces new
identifiers and types (the function prototype).
So in this patch, we have to write the tests as:
```
// partA.cppm
export module m:partA;
export int getA() { ... }
export int getA2(int) { ... }
// partA.v1.cppm
export module m:partA;
export int getA() { ... }
export int getA(int) { ... }
export int getA2(int) { ... }
// partB.cppm
export module m:partB;
export void b() {}
// m.cppm
export module m;
export import :partA;
export import :partB;
// onlyUseB;
export module onlyUseB;
import m;
export inline void onluUseB() {
b();
}
```
so that the new introduced declaration `int getA(int)` doesn't introduce
new identifiers and types, then the BMI of `onlyUseB` can keep
unchanged.
While it looks not so great, the patch should be the base of the patch
to erase the transitive change for identifiers and types since I don't
know how can we introduce new types and identifiers without introducing
new declarations. Given how tightly the relationship between
declarations, types and identifiers, I think we can only reach the ideal
state after we made the series for all of the three entties.
The design of the patch is similar to
https://github.com/llvm/llvm-project/pull/86912, which extends the
32-bit DeclID to 64-bit and use the higher bits to store the module file
index and the lower bits to store the Local Decl ID.
A slight difference is that we only use 48 bits to store the new DeclID
since we try to use the higher 16 bits to store the module ID in the
prefix of Decl class. Previously, we use 32 bits to store the module ID
and 32 bits to store the DeclID. I don't want to allocate additional
space so I tried to make the additional space the same as 64 bits. An
potential interesting thing here is about the relationship between the
module ID and the module file index. I feel we can get the module file
index by the module ID. But I didn't prove it or implement it. Since I
want to make the patch itself as small as possible. We can make it in
the future if we want.
Another change in the patch is the new concept Decl Index, which means
the index of the very big array `DeclsLoaded` in ASTReader. Previously,
the index of a loaded declaration is simply the Decl ID minus
PREDEFINED_DECL_NUMs. So there are some places they got used
ambiguously. But this patch tried to split these two concepts.
As https://github.com/llvm/llvm-project/pull/86912 did, the change will
increase the on-disk PCM file sizes. As the declaration ID may be the
most IDs in the PCM file, this can have the biggest impact on the size.
In my experiments, this change will bring 6.6% increase of the on-disk
PCM size. No compile-time performance regression observed. Given the
benefits in the motivation example, I think the cost is worthwhile.
Commit: df6750eaa80099a1e96439bc060a18a26d7212e6
https://github.com/llvm/llvm-project/commit/df6750eaa80099a1e96439bc060a18a26d7212e6
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/wqm.ll
Log Message:
-----------
[AMDGPU] Fix interaction between WQM and llvm.amdgcn.init.exec (#93680)
Whole quad mode requires inserting a copy of the initial EXEC mask. In a
function that also uses llvm.amdgcn.init.exec, insert the COPY after
initializing EXEC.
Commit: acc927ac2369605c4ec9268d542bb51072d73794
https://github.com/llvm/llvm-project/commit/acc927ac2369605c4ec9268d542bb51072d73794
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[Frontend][OpenMP] Sort all the things in OMP.td, NFC (#94653)
The file OMP.td is becoming tedious to update by hand due to the
seemingly random ordering of various items in it. This patch brings
order to it by sorting most of the contents.
The clause definitions are sorted alphabetically with respect to the
spelling of the clause.[1]
The directive definitions are split into two leaf directives and
compound directives.[2] Within each, definitions are sorted
alphabetically with respect to the spelling, with the exception that
"end xyz" directives are placed immediately following the definition of
"xyz".[3]
Within each directive definition, the lists of clauses are also sorted
alphabetically.
[1] All spellings are made of lowercase letters, _, or space. Ordering
that includes non-letters follows the order assumed by the `sort`
utility.
[2] Compound directives refer to the consituent leaf directives, hence
the leaf definitions must come first.
[3] Some of the "end xyz" directives have properties derived from the
corresponding "xyz" directive. This exception guarantees that "xyz"
precedes the "end xyz".
Commit: 913a8244fe8687df1f27b61c87aa23cf4fcbe84e
https://github.com/llvm/llvm-project/commit/913a8244fe8687df1f27b61c87aa23cf4fcbe84e
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
A flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
A flang/test/Lower/OpenMP/DelayedPrivatization/target-private-simple.f90
Log Message:
-----------
[flang][OpenMP] Lower `target .. private(..)` to `omp.private` ops (#94195)
Extends delayed privatization support to `taraget .. private(..)`. With
this PR, `private` is support for `target` **only** is delayed
privatization mode.
Commit: 2c3723d321ae000dfc9dfab064076799a90c322e
https://github.com/llvm/llvm-project/commit/2c3723d321ae000dfc9dfab064076799a90c322e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCObjectRules.cmake
Log Message:
-----------
[libc] Correctly pass the C++ standard to NVPTX internal builds
Summary:
The NVPTX build wasn't getting the `C++20` standard necessary for a few
files.
Commit: 5b2f7a19711710df1469ab8a0096fe2f8052c8b1
https://github.com/llvm/llvm-project/commit/5b2f7a19711710df1469ab8a0096fe2f8052c8b1
Author: Ryan Holt <ryanholt at mathworks.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/test/Dialect/Linalg/transform-lower-pack.mlir
Log Message:
-----------
[mlir][linalg] Support lowering unpack with outer_dims_perm (#94477)
This commit adds support for lowering `tensor.unpack` with a
non-identity `outer_dims_perm`. This was previously left as a
not-yet-implemented case.
Commit: c886d66da03bdf26e6fca68a1b730ae6eb923194
https://github.com/llvm/llvm-project/commit/c886d66da03bdf26e6fca68a1b730ae6eb923194
Author: Max191 <44243577+Max191 at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
M mlir/test/Dialect/Linalg/reshape_fusion.mlir
Log Message:
-----------
[mlir] Add reshape propagation patterns for tensor.pad (#94489)
This PR adds fusion by collapsing and fusion by expansion patterns for
`tensor.pad` ops in ElementwiseOpFusion. Pad ops can be expanded or
collapsed as long as none of the padded dimensions will be expanded or
collapsed.
Commit: 2117677e304d334326f6591f3c75fb2f34dc4bcb
https://github.com/llvm/llvm-project/commit/2117677e304d334326f6591f3c75fb2f34dc4bcb
Author: Max191 <44243577+Max191 at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir] Fix bugs in expand_shape patterns after semantics changes (#94631)
After the `output_shape` field was added to `expand_shape` ops,
dynamically sized expand shapes are now possible, but this was not
accounted for in the folder. This PR tightens the constraints of the
folder to fix this.
Commit: ac02168990aa8429898d0c59fec7a78526638c5c
https://github.com/llvm/llvm-project/commit/ac02168990aa8429898d0c59fec7a78526638c5c
Author: David Green <david.green at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/CodeGen/ARM/neon_vabd.ll
M llvm/test/CodeGen/ARM/vaba.ll
M llvm/test/CodeGen/ARM/vabd.ll
Log Message:
-----------
[ARM] Clean up neon_vabd.ll, vaba.ll and vabd.ll tests a bit. NFC
Change the target triple to remove some unnecessary instructions.
Commit: 2f0308ed02ea622b8228d271d9aebe4bd4deacdd
https://github.com/llvm/llvm-project/commit/2f0308ed02ea622b8228d271d9aebe4bd4deacdd
Author: Farzon Lotfi <1802579+farzonl at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-tan.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
M llvm/test/CodeGen/AArch64/illegal-float-ops.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-calls-libsystem-darwin.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
Log Message:
-----------
[arm64] Add tan intrinsic lowering (#94545)
This change is an implementation of
https://github.com/llvm/llvm-project/issues/87367's investigation on
supporting IEEE math operations as intrinsics.
Which was discussed in this RFC:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294
This PR is just for Tan.
Now that x86 tan backend landed:
https://github.com/llvm/llvm-project/pull/90503 we can add other
backends since the shared pieces are in tree now.
Changes:
- `llvm/include/llvm/Analysis/VecFuncs.def` - vectorization of tan for
arm64 backends.
- `llvm/lib/Target/AArch64/AArch64FastISel.cpp` - Add tan to the libcall
table
- `llvm/lib/Target/AArch64/AArch64ISelLowering.cpp` - Add tan expansion
for f128, f16, and vector\neon operations
- `llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp` define
`G_FTAN` as a legal arm64 instruction
resolves #94755
Commit: c5fcc2ea55372060760b0ba46d36d03ed39825d5
https://github.com/llvm/llvm-project/commit/c5fcc2ea55372060760b0ba46d36d03ed39825d5
Author: David Green <david.green at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/addp-shuffle.ll
Log Message:
-----------
[AArch64] Add addp from shuffles tests. NFC
Commit: 2981f3a284302bb12b292bcf09e7e09ae2eb696a
https://github.com/llvm/llvm-project/commit/2981f3a284302bb12b292bcf09e7e09ae2eb696a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
Log Message:
-----------
[Clang] Add timeout for GPU detection utilities (#94751)
Summary:
The utilities `nvptx-arch` and `amdgpu-arch` are used to support
`--offload-arch=native` among other utilities in clang. However, these
rely on the GPU drivers to query the features. In certain cases these
drivers can become locked up, which will lead to indefinate hangs on any
compiler jobs running in the meantime.
This patch adds a ten second timeout period for these utilities before
it kills the job and errors out.
Commit: 2afea7296812b7e12c6ec683e6858bd4cbe8dd8d
https://github.com/llvm/llvm-project/commit/2afea7296812b7e12c6ec683e6858bd4cbe8dd8d
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
A llvm/test/CodeGen/RISCV/xcvmem.ll
Log Message:
-----------
[RISCV] Codegen support for XCVmem extension (#76916)
All post-Increment load/store, register-register load/store
spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill,
@NandniJamnadas, @PaoloS02, @serkm, @simonpcook, @xingmingjie, @realqhc
Commit: 3b16630c26505060a876f578e4b2ba701c780e9a
https://github.com/llvm/llvm-project/commit/3b16630c26505060a876f578e4b2ba701c780e9a
Author: Xuan Zhang <144393379+xuanzh-meta at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/MachineOutliner.cpp
A llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll
A llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir
M llvm/test/CodeGen/ARM/machine-outliner-calls.mir
M llvm/test/CodeGen/ARM/machine-outliner-default.mir
M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
Log Message:
-----------
[MachineOutliner] Sort by Benefit to Cost Ratio (#90264)
This PR depends on https://github.com/llvm/llvm-project/pull/90260
We changed the order in which functions are outlined in Machine
Outliner.
The formula for priority is found via a black-box Bayesian optimization
toolbox. Using this formula for sorting consistently reduces the
uncompressed size of large real-world mobile apps. We also ran a few
benchmarks using LLVM test suites, and showed that sorting by priority
consistently reduces the text segment size.
|run (CTMark/) |baseline (1)|priority (2)|diff (1 -> 2)|
|----------------|------------|------------|-------------|
|lencod |349624 |349264 |-0.1030% |
|SPASS |219672 |219480 |-0.0874% |
|kc |271956 |251200 |-7.6321% |
|sqlite3 |223920 |223708 |-0.0947% |
|7zip-benchmark |405364 |402624 |-0.6759% |
|bullet |139820 |139500 |-0.2289% |
|consumer-typeset|295684 |290196 |-1.8560% |
|pairlocalalign |72236 |72092 |-0.1993% |
|tramp3d-v4 |189572 |189292 |-0.1477% |
This is part of an enhanced version of machine outliner -- see
[RFC](https://discourse.llvm.org/t/rfc-enhanced-machine-outliner-part-1-fulllto-part-2-thinlto-nolto-to-come/78732).
Commit: eb33e462ba536735b3d8449a81009a253f0f43bc
https://github.com/llvm/llvm-project/commit/eb33e462ba536735b3d8449a81009a253f0f43bc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
[memprof] Clean up IndexedMemProfReader (NFC) (#94710)
Parameter "Version" is confusing in deserializeV012 and deserializeV3
because we also have member variable "Version". Fortunately,
parameter "Version" and member variable "Version" always have the same
value because IndexedMemProfReader::deserialize initializes the member
variable and passes it to deserializeV012 and deserializeV3.
This patch removes the parameter.
Commit: 55bdb36e39670d07aaaf04a24783a2008e8e60dd
https://github.com/llvm/llvm-project/commit/55bdb36e39670d07aaaf04a24783a2008e8e60dd
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/BoxValue.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/HLFIR/assumed-rank-inquiries-2.f90
Log Message:
-----------
[flang] lower SIZE and SIZEOF for assumed-ranks (#94684)
Commit: c348e265bd1284f770e66639633199fefd8015ec
https://github.com/llvm/llvm-project/commit/c348e265bd1284f770e66639633199fefd8015ec
Author: Kazu Hirata <kazu at google.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
Log Message:
-----------
[memprof] Use CallStackRadixTreeBuilder in the V3 format (#94708)
This patch integrates CallStackRadixTreeBuilder into the V3 format,
reducing the profile size to about 27% of the V2 profile size.
- Serialization: writeMemProfCallStackArray just needs to write out
the radix tree array prepared by CallStackRadixTreeBuilder.
Mappings from CallStackIds to LinearCallStackIds are moved by new
function CallStackRadixTreeBuilder::takeCallStackPos.
- Deserialization: Deserializing a call stack is the same as
deserializing an array encoded in the obvious manner -- the length
followed by the payload, except that we need to follow a pointer to
the parent to take advantage of common prefixes once in a while.
This patch teaches LinearCallStackIdConverter to how to handle those
pointers.
Commit: 7d69095fd50b7ef35282f83a9263bb8027ad521b
https://github.com/llvm/llvm-project/commit/7d69095fd50b7ef35282f83a9263bb8027ad521b
Author: Mubashar Ahmad <mubashar.ahmad at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
R mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg
R mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/test-setArmSVLBits.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir
R mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
R mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-scalable-deinterleave.mlir
R mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-deinterleave.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-setArmVLBits.mlir
M mlir/test/lit.cfg.py
Log Message:
-----------
[mlir][vector] Remove Emulated Sub-directory (#94742)
The "Emulated" sub-directories under "ArmSVE" and
"ArmSME" have been removed. Associated tests
have been moved up a directory and now include
the "REQUIRES" constraint for the arm-emulator.
Commit: d099d6c76b3216b30b30de22cccf155fcc9e1c51
https://github.com/llvm/llvm-project/commit/d099d6c76b3216b30b30de22cccf155fcc9e1c51
Author: Nico Weber <thakis at chromium.org>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/test/BUILD.gn
Log Message:
-----------
[gn] port 33a6ce18373ff (check-clang obj2yaml dep)
Commit: fc95645e37f244c2fc155f1ee51047f90329e8c1
https://github.com/llvm/llvm-project/commit/fc95645e37f244c2fc155f1ee51047f90329e8c1
Author: Nico Weber <thakis at chromium.org>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-config/BUILD.gn
Log Message:
-----------
[gn] port cb7690af09b95 (ntdll dep)
Commit: b25b1db8199d86cb3645e92200cda8d5d30922d0
https://github.com/llvm/llvm-project/commit/b25b1db8199d86cb3645e92200cda8d5d30922d0
Author: c8ef <c8ef at outlook.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/Support/KnownBits.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/unittests/IR/DemandedBitsTest.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
M llvm/unittests/Support/KnownBitsTest.h
Log Message:
-----------
[KnownBits] Remove `hasConflict()` assertions (#94568)
Allow KnownBits to represent "always poison" values via conflict.
close: #94436
Commit: 790992dd4018f55479a2c53a79088cb37710c85b
https://github.com/llvm/llvm-project/commit/790992dd4018f55479a2c53a79088cb37710c85b
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
Log Message:
-----------
[libc++][test][AIX] Only XFAIL atomic tests for before clang 19 (#94646)
These tests pass on 64-bit. They were fixed by 5fdd094837c6 on 32-bit.
So XFAIL only for 32-bit before clang 19.
Commit: f7018ba0eeaad8dc3e1917cfb986fc9689d72e85
https://github.com/llvm/llvm-project/commit/f7018ba0eeaad8dc3e1917cfb986fc9689d72e85
Author: David Green <david.green at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/arm64-uzp.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
Log Message:
-----------
[AArch64] Add patterns for add(uzp1(x,y), uzp2(x, y)) -> addp.
If we are extracting the even lanes and the odd lanes and adding them, we can
use an addp instruction.
Commit: 4f9c0fa22374d50643177adc4fb2706fa4b9b163
https://github.com/llvm/llvm-project/commit/4f9c0fa22374d50643177adc4fb2706fa4b9b163
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
Log Message:
-----------
[LV] Add test with dead load and vector pointer.
Commit: e9adcc488f96a9f2b8c4344f5e3c7ca6639b9562
https://github.com/llvm/llvm-project/commit/e9adcc488f96a9f2b8c4344f5e3c7ca6639b9562
Author: Konstantin Varlamov <varconsteq at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libcxx/include/regex
A libcxx/test/std/re/re.alg/re.alg.replace/zero_length_matches.pass.cpp
M libcxx/test/std/re/re.iter/re.regiter/re.regiter.incr/post.pass.cpp
Log Message:
-----------
[libc++][regex] Correctly adjust match prefix for zero-length matches. (#94550)
For regex patterns that produce zero-length matches, there is one
(imaginary) match in-between every character in the sequence being
searched (as well as before the first character and after the last
character). It's easiest to demonstrate using replacement:
`std::regex_replace("abc"s, "!", "")` should produce `!a!b!c!`, where
each exclamation mark makes a zero-length match visible.
Currently our implementation doesn't correctly set the prefix of each
zero-length match, "swallowing" the characters separating the imaginary
matches -- e.g. when going through zero-length matches within `abc`, the
corresponding prefixes should be `{'', 'a', 'b', 'c'}`, but before this
patch they will all be empty (`{'', '', '', ''}`). This happens in the
implementation of `regex_iterator::operator++`. Note that the Standard
spells out quite explicitly that the prefix might need to be adjusted
when dealing with zero-length matches in
[`re.regiter.incr`](http://eel.is/c++draft/re.regiter.incr):
> In all cases in which the call to `regex_search` returns `true`,
`match.prefix().first` shall be equal to the previous value of
`match[0].second`... It is unspecified how the implementation makes
these adjustments.
[Reproduction example](https://godbolt.org/z/8ve6G3dav)
```cpp
#include <iostream>
#include <regex>
#include <string>
int main() {
std::string str = "abc";
std::regex empty_matching_pattern("");
{ // The underlying problem is that `regex_iterator::operator++` doesn't update
// the prefix correctly.
std::sregex_iterator i(str.begin(), str.end(), empty_matching_pattern), e;
std::cout << "\"";
for (; i != e; ++i) {
const std::ssub_match& prefix = i->prefix();
std::cout << prefix.str();
}
std::cout << "\"\n";
// Before the patch: ""
// After the patch: "abc"
}
{ // `regex_replace` makes the problem very visible.
std::string replaced = std::regex_replace(str, empty_matching_pattern, "!");
std::cout << "\"" << replaced << "\"\n";
// Before the patch: "!!!!"
// After the patch: "!a!b!c!"
}
}
```
Fixes #64451
rdar://119912002
Commit: 35fa2ded2ac52151be22c206fc92b983d1fd8e30
https://github.com/llvm/llvm-project/commit/35fa2ded2ac52151be22c206fc92b983d1fd8e30
Author: Vy Nguyen <oontvoo at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
Reapply PR/87550 (#94625)
Re-apply https://github.com/llvm/llvm-project/pull/87550 with fixes.
Details:
Some tests in fuchsia failed because of the newly added assertion.
This was because `GetExceptionBreakpoint()` could be called before
`g_dap.debugger` was initted.
The fix here is to just lazily populate the list in
GetExceptionBreakpoint() rather than assuming it's already been initted.
(There is some nuisance here because we can't simply just populate it in
DAP::DAP(), which is a global ctor and is called before
`SBDebugger::Initialize()` is called. )
Commit: 716ed5fccd2a960981fec2c5acb17292a1502435
https://github.com/llvm/llvm-project/commit/716ed5fccd2a960981fec2c5acb17292a1502435
Author: Nico Weber <thakis at chromium.org>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx20.rst
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/docs/UsingLibcxx.rst
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/memory
M libcxx/modules/std/memory.inc
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_strong.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_strong_explicit.depr_in_cxx20.verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_weak.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_weak_explicit.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_exchange.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_exchange_explicit.verify.depr_in_cxx20..cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_is_lock_free.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_load.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_load_explicit.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_store.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_store_explicit.depr_in_cxx20..verify.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_strong.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_strong_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_weak.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_weak_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_exchange.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_exchange_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_is_lock_free.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_load.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_load_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_store.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_store_explicit.pass.cpp
Log Message:
-----------
[libc++] Undeprecate shared_ptr atomic access APIs (#92920)
This patch reverts 9b832b72 (#87111):
- [libc++] Deprecated `shared_ptr` Atomic Access APIs as per P0718R2
- [libc++] Implemented P2869R3: Remove Deprecated `shared_ptr` Atomic Access APIs from C++26
As explained in [1], the suggested replacement in P2869R3 is `__cpp_lib_atomic_shared_ptr`,
which libc++ does not yet implement. Let's not deprecate the old way of doing things before
the new way of doing things exists.
[1]: https://github.com/llvm/llvm-project/pull/87111#issuecomment-2112740039
Commit: 97b12df2cc27e1ef376692a0c5b62e1f2e793970
https://github.com/llvm/llvm-project/commit/97b12df2cc27e1ef376692a0c5b62e1f2e793970
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/Transforms/Reassociate/shifttest.ll
Log Message:
-----------
[Reassociate] shifttest.ll - generate test checks to replace custom grep expression
(and remove an unused argument)
Commit: b01ac5137c28fa5e1b44a5d850cb7a6ace7d8799
https://github.com/llvm/llvm-project/commit/b01ac5137c28fa5e1b44a5d850cb7a6ace7d8799
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M flang/include/flang/Runtime/inquiry.h
M flang/runtime/inquiry.cpp
M flang/unittests/Runtime/Inquiry.cpp
Log Message:
-----------
[flang][runtime] add SHAPE runtime interface (#94702)
Add SHAPE runtime API (will be used for assumed-rank, lowering is
generating other cases inline).
I tried to make it in a way were there is no dynamic allocation in the
runtime/deallocation expected to be inserted by inline code for arrays
that we know are small (lowering will just always stack allocate a rank
15 array to avoid dynamic stack allocation or heap allocation).
Commit: 1539da4601448711fcfa622e26e596973d58c670
https://github.com/llvm/llvm-project/commit/1539da4601448711fcfa622e26e596973d58c670
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
M flang/test/Lower/OpenMP/DelayedPrivatization/target-private-simple.f90
Log Message:
-----------
[flang][OpenMP] Add `--openmp-enable-delayed-privatization-staging` flag (#94749)
Commit: 374f6554c3e409e4b9b5fd0ec90c5272768f5ab9
https://github.com/llvm/llvm-project/commit/374f6554c3e409e4b9b5fd0ec90c5272768f5ab9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
Log Message:
-----------
[OpenMP] Fix passing target id features to AMDGPU offloading (#94765)
Summary:
AMDGPU supports a `target-id` feature which is used to qualify targets
with different incompatible features. These are both rules and target
features. Currently, we pass `-target-cpu` twice when offloading to
OpenMP, and do not pass the target-id features at all. The effect was
that passing something like `--offload-arch=gfx90a:xnack+` would show up
as `-target-cpu=gfx90a:xnack+ -target-cpu=gfx90a`. Thus ignoring the
xnack completely and passing it twice. This patch fixes that to pass it
once and then separate it like how HIP does.
Commit: bbddedb3bf7b17c5caa4732c4a94dde8824c5e3a
https://github.com/llvm/llvm-project/commit/bbddedb3bf7b17c5caa4732c4a94dde8824c5e3a
Author: kper <kper at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/test/CXX/basic/basic.lookup/basic.lookup.elab/p2.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.elab/p2-0x.cpp
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/temp/temp.decls/temp.friend/p1.cpp
M clang/test/CXX/temp/temp.spec/no-body.cpp
M clang/test/SemaCXX/PR8755.cpp
M clang/test/SemaCXX/using-decl-templates.cpp
M clang/test/SemaTemplate/template-id-expr.cpp
Log Message:
-----------
Fixed grammatical error in "enum specifier" error msg #94443 (#94592)
As discussed in #94443, this PR changes the wording to be more correct.
Commit: b59567b99a44e9fe423e8712123f864b0c83eebc
https://github.com/llvm/llvm-project/commit/b59567b99a44e9fe423e8712123f864b0c83eebc
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaTemplate/cwg2398.cpp
Log Message:
-----------
[clang] always use resolved arguments for default argument deduction (#94756)
Commit: c467e6097e7332b65f9390e7088cb7ae0116a8bb
https://github.com/llvm/llvm-project/commit/c467e6097e7332b65f9390e7088cb7ae0116a8bb
Author: Jan Voung <jvoung at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
Check if LLD is built when checking if lto_supported (#92752)
Otherwise, older copies of LLD may not understand the latest bitcode
versions (for example, if we increase
`ModuleSummaryIndex::BitCodeSummaryVersion`)
Related to
https://github.com/llvm/llvm-project/pull/90692#issuecomment-2113250317
Commit: b653357141030620ce3e70ea939efbcb71d40657
https://github.com/llvm/llvm-project/commit/b653357141030620ce3e70ea939efbcb71d40657
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/test/Dialect/Vector/vector-transfer-flatten.mlir
Log Message:
-----------
[mlir][vector][NFC] Make function name more meaningful in lit tests. (#94538)
It also moves the test near other similar test cases.
Commit: 0605e984fab700a6ef4affc3fdb66aaba3417baa
https://github.com/llvm/llvm-project/commit/0605e984fab700a6ef4affc3fdb66aaba3417baa
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
A llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/ARM/arm-half-promote.ll
A llvm/test/CodeGen/X86/select-phi-s16-fp.ll
Log Message:
-----------
[SDISel][Builder] Fix the instantiation of <1 x bfloat|half> (#94591)
Prior to this change, `SelectionDAGBuilder` was producing `SDNode`s of
the form: `f32 = extract_vector_elt <1 x bfloat|half>, i32 0` when
lowering phis of `<1 x bfloat|half>` and running on a target that
promotes this type to `f32` (like some x86 or AMDGPU targets.)
This construct is invalid since this type of node only allows type
extensions for integer types.
It went unotice because the `extract_vector_elt` node is later broken
down in `bitcast` followed by `bf16_to_fp|fp_extend`. However, when the
argument of the phi is a constant we were crashing because the existing
code would try to constant fold this `extract_vector_elt` into a
any_ext.
This patch fixes this by using a proper decomposition for `<1 x
bfloat|half>`:
```
bfloat|half = bitcast <1 x blfoat|half>
float = fp_extend bfloat|half
```
This change should be NFC for the non-constant-folding cases and fix the
SDISel crashes (reported in
https://github.com/llvm/llvm-project/issues/94449) for the folding
cases.
Note: The change on the arm test is a missing fp16 to f32 constant folding
exposed by this patch. I'll push a separate improvement for that.
Commit: e9fa6ffaf7e86fe9f91fbcaabce5436311ac814c
https://github.com/llvm/llvm-project/commit/e9fa6ffaf7e86fe9f91fbcaabce5436311ac814c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
Log Message:
-----------
[RISCV] Fold (vXi8 (trunc (vselect (setltu, X, 256), X, (sext (setgt X, 0))))) to vmax+vnclipu. (#94720)
This pattern is an obscured way to express saturating a signed value
into a smaller unsigned value.
If (setltu, X, 256) is true, then the value is already in the desired
range so we can pick X. If it's false, we select (sext (setgt X, 0))
which is 0 for negative values and all ones for positive values. The all
ones value when truncated to the final type will still be all ones like
we want.
Commit: cce10cc4583e7294950f4cfa4b8364d54c32241c
https://github.com/llvm/llvm-project/commit/cce10cc4583e7294950f4cfa4b8364d54c32241c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/test/MC/RISCV/insn.s
M llvm/test/MC/RISCV/insn_c.s
Log Message:
-----------
[RISCV] Add .insn alias for addresses without the leading immediate. (#94698)
Most other instructions accept addresses that start with a '(' without
an immediate before it. The .insn cases were missing. This is also
supported by binutils.
Commit: adcf33f8fbcc0f068bd4b8254994b16dda525009
https://github.com/llvm/llvm-project/commit/adcf33f8fbcc0f068bd4b8254994b16dda525009
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/Symbol/TypeSystem.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/Symbol/TypeSystem.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
Revert "Reapply PR/87550 (#94625)"
This reverts commit 35fa2ded2ac52151be22c206fc92b983d1fd8e30.
It broke the LLDB bots on green dragon
Commit: e5648525fd041fe577c65cc392c73040e60fed60
https://github.com/llvm/llvm-project/commit/e5648525fd041fe577c65cc392c73040e60fed60
Author: David Green <david.green at arm.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/addp-shuffle.ll
Log Message:
-----------
[AArch64] Add patterns for fadd(uzp1(x,y), uzp2(x, y)) -> faddp.
Similar to f7018ba0eeaad8dc3e1917cfb986fc9689d72e85, this adds patterns for
floating point faddp from an fadd and shuffles.
Commit: f9ae07b9e1509732be01fddefb529c6626c119a9
https://github.com/llvm/llvm-project/commit/f9ae07b9e1509732be01fddefb529c6626c119a9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libcxx/include/deque
M libcxxabi/src/aix_state_tab_eh.inc
Log Message:
-----------
[libc++][NFC] Fix typo
Commit: 6f2c61071c274a1b5e212e6ad4114641ec7c7fc3
https://github.com/llvm/llvm-project/commit/6f2c61071c274a1b5e212e6ad4114641ec7c7fc3
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/Analysis/LazyCallGraph.h
M llvm/lib/Analysis/CGSCCPassManager.cpp
M llvm/lib/Analysis/LazyCallGraph.cpp
Log Message:
-----------
[CGSCC] Verify that call graph is valid after iteration (#94692)
Only in expensive checks, to match other LazyCallGraph verification.
Is helpful for verifying LazyCallGraph updates. Many issues only surface
when we reuse the LazyCallGraph.
Commit: 66df6141659375e738d9b9b74bf79b2317576042
https://github.com/llvm/llvm-project/commit/66df6141659375e738d9b9b74bf79b2317576042
Author: Augusto Noronha <augusto2112 at me.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/test/CodeGen/debug-info-packed-struct.c
M clang/test/CodeGenCXX/debug-info-struct-align.cpp
Log Message:
-----------
Fix #pragma (packed, n) not emitting the alignment in debug info (#94673)
Debug info generation won't emit the alignment of types that have a
standard alignment. It was not taking into account the that case.
rdar://127785973
Commit: 2c047e67a5bfb479d7422f5b270e7f90ae037508
https://github.com/llvm/llvm-project/commit/2c047e67a5bfb479d7422f5b270e7f90ae037508
Author: Nico Weber <thakis at chromium.org>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/CXX/dcl.dcl/basic.namespace/namespace.udecl/p6-cxx11.cpp
M clang/test/CXX/drs/cwg4xx.cpp
Log Message:
-----------
[clang] Add fixit for using declaration with a (qualified) namespace (#94762)
For `using std::literals`, we now output:
error: using declaration cannot refer to a namespace
4 | using std::literals;
| ~~~~~^
note: did you mean 'using namespace'?
4 | using std::literals;
| ^
| namespace
Previously, we didn't have the note.
This only fires for qualified namespaces. Just `using std;` doesn't
trigger this, since using declarations without cxx scope specifier are
rejected earlier. Making that work is an exercise for future selves :)
Commit: 11d643f0b11c041d7030d43a328adf2eb3ba4e3d
https://github.com/llvm/llvm-project/commit/11d643f0b11c041d7030d43a328adf2eb3ba4e3d
Author: Michael Jones <michaelrj at google.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/baremetal/CMakeLists.txt
A libc/src/stdio/baremetal/printf.cpp
M libc/src/stdio/generic/CMakeLists.txt
A libc/src/stdio/generic/printf.cpp
A libc/src/stdio/generic/vprintf.cpp
R libc/src/stdio/printf.cpp
R libc/src/stdio/vprintf.cpp
Log Message:
-----------
[libc] Add baremetal printf (#94078)
For baremetal targets that don't support FILE, this version of printf
just writes directly to a function provided by a vendor. To do this both
printf and vprintf were moved to /generic (vprintf since they need the
same flags and cmake gets funky about setting variables in one file and
reading them in another).
Commit: e20b90472160e47112886d959bbe0bbeff50b8ee
https://github.com/llvm/llvm-project/commit/e20b90472160e47112886d959bbe0bbeff50b8ee
Author: Lei Wang <wlei at fb.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/PseudoProbe.h
M llvm/lib/IR/PseudoProbe.cpp
M llvm/lib/Transforms/IPO/SampleProfileProbe.cpp
M llvm/test/Transforms/SampleProfile/pseudo-probe-discriminator.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-verify.ll
Log Message:
-----------
[PseudoProbe] Make probe discriminator compatible with dwarf base discriminator (#94506)
It's useful if the probe-based build can consume a dwarf based
profile(e.g. the profile transition), before there is a conflict for the
discriminator, this change tries to mitigate the issue by encoding the
dwarf base discriminator into the probe discriminator.
As the num of probe id(num of basic block and calls) starts from 1,
there are some unused space. We try to reuse some bit of the probe id.
The new encode rule is:
- Use a bit to [28:28] to indicate whether dwarf base discriminator is
encoded.(fortunately we can borrow this bit from the `PseudoProbeType`)
- If the bit is set, use [15:3] for probe id, [18:16] for dwarf base
discriminator. Otherwise, still use [18:3] for probe id.
Note that these doesn't affect the original probe id capacity, we still
prioritize probe id encoding, i.e. the base discriminator is not encoded
when probe id is bigger than [15:3].
Then adjust `getBaseDiscriminatorFromDiscriminator` to use the base
discriminator from the probe discriminator.
Commit: c3a50879dfca9ab06ebfe52f48019bb6ac40bb4d
https://github.com/llvm/llvm-project/commit/c3a50879dfca9ab06ebfe52f48019bb6ac40bb4d
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/test/Driver/gcc-param.c
Log Message:
-----------
[Driver,test] Add -Wno-msvc-not-found to gcc-param.c
Fixes: 56c4971d33230607a7329bb831b6c8588231e872
If the default target triple uses visualstudio::Linker::ConstructJob,
when a MSVC installation cannot be found, there will be a
-Wmsvc-not-found diagnostic, which is turned to an error due to -Werror.
We have many driver tests that don't specify --target= and would get a
-Wmsvc-not-found warning, but this might be the only that uses -Werror
and is not skipped by a `UNSUPPORTED`.
Commit: bd6e324b67cdadde2593327753e99782146d9bf8
https://github.com/llvm/llvm-project/commit/bd6e324b67cdadde2593327753e99782146d9bf8
Author: walkerkd <56538734+walkerkd at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/Driver/ToolChains/BareMetal.cpp
A clang/test/Driver/baremetal-ld.c
Log Message:
-----------
[clang][driver] Enable '-flto' on bare-metal (#94738)
Pass the linker LTO options enabled by the clang '-flto' command line
options when targeting bare-metal.
---------
Co-authored-by: Keith Walker <keith.walker at arm.com>
Commit: d3bcd9b16badac301d4f29cf401387ae5e14999f
https://github.com/llvm/llvm-project/commit/d3bcd9b16badac301d4f29cf401387ae5e14999f
Author: Brad Smith <brad at comstyle.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/tools/llvm-jitlink/CMakeLists.txt
Log Message:
-----------
[CMake] Fix building on Haiku (#94721)
Needed for getaddrinfo().
Commit: 9a737109a07c0c29176e617eed34e91b523b7e9b
https://github.com/llvm/llvm-project/commit/9a737109a07c0c29176e617eed34e91b523b7e9b
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll
A llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-simple-for.ll
A llvm/test/CodeGen/SPIRV/transcoding/bitcast-diff-addrspace.ll
Log Message:
-----------
[SPIR-V] Improve type inference, addrspacecast and dependencies between SPIR-V entities and required capability/extensions (#94626)
This PR continues https://github.com/llvm/llvm-project/pull/94467 and
contains fixes in emission of type intrinsics, constant recording and
corresponding test cases:
* type-deduce-global-dup.ll -- fix of integer constant emission on
32-bit platforms and correct type deduction for globals
* type-deduce-simple-for.ll -- fix of GEP translation (there was an
issue previously that led to incorrect translation/broken logic of
for-range implementation)
This PR also:
* fixes a cast between identical storage classes and updates the test
case to include validation run by spirv-val,
* ensures that Bitcast for pointers satisfies the requirement that the
address spaces must match and adds the corresponding test case,
* improve encode in Tablegen and decode in code of dependencies between
SPIR-V entities and required capability/extensions,
* prevent emission of identical OpTypePointer instructions.
Commit: 4196c185b12b38499e132a50b14aa1977004f02c
https://github.com/llvm/llvm-project/commit/4196c185b12b38499e132a50b14aa1977004f02c
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port #94078 (#94792)
Commit: 28dd55b97372271591d7802fd7b7eede0832aaa9
https://github.com/llvm/llvm-project/commit/28dd55b97372271591d7802fd7b7eede0832aaa9
Author: Gábor Spaits <gaborspaits1 at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32-libcall.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64-libcall.mir
Log Message:
-----------
[RISCV][GISel] Do libcall for G_FPTOSI, G_FPTOUI when no D or F support (#94613)
When compiling the following code:
```cpp
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include <stdbool.h>
int main() {
int a;
float f;
scanf("%d", &a);
scanf("%f", &f);
a += (int)f;
return a;
}
```
for `-march=rv32ima_zbb` we get a libcall:
```
call scanf
lw a0, -20(s0)
call __fixsfsi
mv a1, a0
```
When we try to use GlobalISel we get this error:
```
error in backend: unable to legalize instruction: %9:_(s32) = G_FPTOSI %8:_(s32) (in function: main)
```
(Here is a link to a reproducer in Godblot:
https://godbolt.org/z/f67vEEb41 )
The goal of this PR is to do a libcall for the legalization of
`G_FPTOSI` and `G_FPTOUI` instead of doing a fallback to Selection DAG
to do the same libcall later.
Commit: c6e9371cbd23a9f2d03fee9b406065dbd0b7cf6a
https://github.com/llvm/llvm-project/commit/c6e9371cbd23a9f2d03fee9b406065dbd0b7cf6a
Author: mgschossmann <109181247+mgschossmann at users.noreply.github.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
A llvm/test/DebugInfo/dwarfdump-loclist-basetyperef.test
Log Message:
-----------
[llvm-dwarfdump] Add a null-check in `prettyPrintBaseTypeRef`. (#93156)
Fixes #93104
Prevent a crash by only printing DWARFUnit-unaware information in cases
in which `DWARFUnit* U` is `nullptr`.
Commit: 27084f73e3b51fa507d1459042eb73e4f7098d73
https://github.com/llvm/llvm-project/commit/27084f73e3b51fa507d1459042eb73e4f7098d73
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/icmp-equality-xor.ll
Log Message:
-----------
[InstCombine] Add tests for folding `(icmp eq/ne (xor x, C0), C1)`; NFC
Commit: 166c1849d6da1577b49305371db1cdfacbb150e4
https://github.com/llvm/llvm-project/commit/166c1849d6da1577b49305371db1cdfacbb150e4
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-equality-xor.ll
M llvm/test/Transforms/InstCombine/icmp-or.ll
M llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Fold `(icmp eq/ne (xor x, y), C1)` even if multiuse
Two folds unlocked:
`(icmp eq/ne (xor x, C0), C1)` -> `(icmp eq/ne x, C2)`
`(icmp eq/ne (xor x, y), 0)` -> `(icmp eq/ne x, y)`
This fixes regressions assosiated with #87180
Closes #87275
Commit: 89c92b0bcf4b9a283ed594e01a4addd90e5d8735
https://github.com/llvm/llvm-project/commit/89c92b0bcf4b9a283ed594e01a4addd90e5d8735
Author: estewart08 <ethan.stewart at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M offload/CMakeLists.txt
M openmp/CMakeLists.txt
Log Message:
-----------
[OpenMP][Offload] - Ensure OPENMP_STANDALONE_BUILD is defined (#94801)
Without a value set conditional checks like
if(NOT ${OPENMP_STANDALONE_BUILD})
will not be able to evaluate to true.
Fixes issue introduced from PR #93463, which did not allow the OMPT
variable to be propogated up to offload during a runtimes build.
Commit: 75b89cc00c0dcc5694c94dd553c5c5204e2e4192
https://github.com/llvm/llvm-project/commit/75b89cc00c0dcc5694c94dd553c5c5204e2e4192
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/pow-1.ll
Log Message:
-----------
InstCombine: Fix testing of pow libcall in errno case (#94772)
There were some tests in this file with "noerrno" in the name, but all
the tests were no errno since all the libcalls were declared with
memory(none). Ensure we have adequate coverage for the errno and
no-errno cases by duplicating the libcall transform cases into errno and
non-errno versions with callsite attributes.
Commit: 96d01a350ce9875a8f893ecdc1d470caf7ed5bcd
https://github.com/llvm/llvm-project/commit/96d01a350ce9875a8f893ecdc1d470caf7ed5bcd
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M lldb/source/Expression/DWARFExpression.cpp
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/ObjectYAML/DWARFYAML.h
M llvm/lib/BinaryFormat/Dwarf.cpp
Log Message:
-----------
[lldb] Encode operands and arity in Dwarf.def and use them in LLDB. (#94679)
This PR extends Dwarf.def to include the number of operands and the arity (the
number of entries on the DWARF stack).
- The arity is used in LLDB's DWARF expression evaluator.
- The number of operands is unused, but is present in the table to avoid
confusing the arity with the operands. Keeping the latter up to date should
be straightforward as it maps directly to a table present in the DWARF
standard.
Commit: 37e309f1635404bfca029c3712ee227a892cd4cf
https://github.com/llvm/llvm-project/commit/37e309f1635404bfca029c3712ee227a892cd4cf
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
A llvm/include/llvm/Transforms/Vectorize/LoopIdiomVectorize.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AArch64/AArch64.h
R llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp
R llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.h
R llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
M llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll
Log Message:
-----------
[AArch64][LoopIdiom] Generalize AArch64LoopIdiomTransform into LoopIdiomVectorize (#94081)
To facilitate sharing LoopIdiomTransform between AArch64 and RISC-V,
this first patch moves AArch64LoopIdiomTransform from lib/Target/AArch64
to lib/Transforms/Vectorize and renames it to LoopIdiomVectorize. The
following patch (#94082) will teach LoopIdiomVectorize how to generate VP
intrinsics (in addition to the current masked vector style) in favor of
RVV.
Commit: 892723662178f22295237a07f1c039abe6c49da0
https://github.com/llvm/llvm-project/commit/892723662178f22295237a07f1c039abe6c49da0
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M .github/workflows/release-binaries.yml
M bolt/include/bolt/Core/MCPlusBuilder.h
M bolt/lib/Passes/VeneerElimination.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M clang-tools-extra/clangd/FindSymbols.cpp
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/clangd/refactor/Rename.cpp
M clang-tools-extra/clangd/unittests/PreambleTests.cpp
M clang-tools-extra/clangd/unittests/XRefsTests.cpp
M clang/cmake/caches/Release.cmake
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTUnresolvedSet.h
M clang/include/clang/AST/DeclAccessPair.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclID.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/Serialization/ModuleManager.h
M clang/include/clang/Tooling/Syntax/Tokens.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/EvalEmitter.cpp
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/MemberPointer.h
M clang/lib/AST/Interp/Opcodes.td
M clang/lib/AST/Interp/Pointer.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ModuleFile.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp
A clang/lib/StaticAnalyzer/Checkers/NoOwnershipChangeVisitor.cpp
A clang/lib/StaticAnalyzer/Checkers/NoOwnershipChangeVisitor.h
M clang/lib/Tooling/Syntax/Tokens.cpp
M clang/test/AST/Interp/cxx20.cpp
M clang/test/AST/Interp/lambda.cpp
M clang/test/CXX/basic/basic.lookup/basic.lookup.elab/p2.cpp
M clang/test/CXX/dcl.dcl/basic.namespace/namespace.udecl/p6-cxx11.cpp
M clang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.elab/p2-0x.cpp
M clang/test/CXX/drs/cwg2xx.cpp
M clang/test/CXX/drs/cwg4xx.cpp
M clang/test/CXX/temp/temp.decls/temp.friend/p1.cpp
M clang/test/CXX/temp/temp.spec/no-body.cpp
M clang/test/CodeGen/debug-info-packed-struct.c
M clang/test/CodeGen/target-data.c
A clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
A clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu
M clang/test/CodeGenCUDA/long-double.cu
A clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu
M clang/test/CodeGenCXX/debug-info-struct-align.cpp
A clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp
M clang/test/CodeGenHIP/hipspv-addr-spaces.cpp
A clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp
A clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
A clang/test/CodeGenHIP/spirv-amdgcn-half.hip
M clang/test/CodeGenOpenCL/amdgcn-flat-scratch-name.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl
M clang/test/Driver/amdgpu-openmp-toolchain.c
A clang/test/Driver/baremetal-ld.c
M clang/test/Driver/gcc-param.c
M clang/test/Misc/target-invalid-cpu-note.c
A clang/test/Modules/no-transitive-decls-change.cppm
M clang/test/Preprocessor/hash_builtin.cpp
M clang/test/Preprocessor/predefined-macros-no-warnings.c
M clang/test/Preprocessor/predefined-macros.c
A clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp
A clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl
M clang/test/SemaCUDA/allow-int128.cu
M clang/test/SemaCUDA/amdgpu-f128.cu
M clang/test/SemaCUDA/float16.cu
M clang/test/SemaCUDA/fp16-arg-return.cu
A clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu
M clang/test/SemaCXX/PR8755.cpp
M clang/test/SemaCXX/using-decl-templates.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx940-param.cl
M clang/test/SemaTemplate/cwg2398.cpp
M clang/test/SemaTemplate/template-id-expr.cpp
M clang/unittests/Interpreter/InterpreterTest.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
M compiler-rt/test/lit.common.cfg.py
M flang/include/flang/Optimizer/Builder/BoxValue.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Runtime/inquiry.h
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Transforms/VScaleAttr.cpp
M flang/runtime/inquiry.cpp
A flang/test/Lower/HLFIR/assumed-rank-inquiries-2.f90
A flang/test/Lower/OpenMP/DelayedPrivatization/target-private-allocatable.f90
A flang/test/Lower/OpenMP/DelayedPrivatization/target-private-multiple-variables.f90
A flang/test/Lower/OpenMP/DelayedPrivatization/target-private-simple.f90
M flang/unittests/Runtime/Inquiry.cpp
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/baremetal/CMakeLists.txt
A libc/src/stdio/baremetal/printf.cpp
M libc/src/stdio/generic/CMakeLists.txt
A libc/src/stdio/generic/printf.cpp
A libc/src/stdio/generic/vprintf.cpp
R libc/src/stdio/printf.cpp
R libc/src/stdio/vprintf.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx20.rst
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/docs/UsingLibcxx.rst
M libcxx/include/__memory/shared_ptr.h
M libcxx/include/deque
M libcxx/include/memory
M libcxx/include/regex
M libcxx/modules/std/memory.inc
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_strong.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_strong_explicit.depr_in_cxx20.verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_weak.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_compare_exchange_weak_explicit.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_exchange.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_exchange_explicit.verify.depr_in_cxx20..cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_is_lock_free.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_load.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_load_explicit.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_store.depr_in_cxx20..verify.cpp
R libcxx/test/libcxx/depr/depr.util.smartptr.shared.atomic/atomic_store_explicit.depr_in_cxx20..verify.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
A libcxx/test/std/re/re.alg/re.alg.replace/zero_length_matches.pass.cpp
M libcxx/test/std/re/re.iter/re.regiter/re.regiter.incr/post.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_strong.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_strong_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_weak.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_compare_exchange_weak_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_exchange.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_exchange_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_is_lock_free.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_load.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_load_explicit.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_store.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared.atomic/atomic_store_explicit.pass.cpp
M libcxxabi/src/aix_state_tab_eh.inc
M lld/docs/ReleaseNotes.rst
M lldb/source/Expression/DWARFExpression.cpp
M llvm/docs/Benchmarking.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/SPIRVUsage.rst
M llvm/include/llvm/Analysis/LazyCallGraph.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/PseudoProbe.h
M llvm/include/llvm/ObjectYAML/DWARFYAML.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Support/KnownBits.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/ARMTargetParser.def
A llvm/include/llvm/Transforms/Vectorize/LoopIdiomVectorize.h
M llvm/lib/Analysis/CGSCCPassManager.cpp
M llvm/lib/Analysis/LazyCallGraph.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
M llvm/lib/CodeGen/MachineOutliner.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetOptionsImpl.cpp
M llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/PseudoProbe.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
R llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp
R llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.h
R llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/CMakeLists.txt
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMFeatures.td
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/lib/Target/ARM/ARMProcessors.td
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/IPO/SampleProfileProbe.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-tan.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/addp-shuffle.ll
M llvm/test/CodeGen/AArch64/arm64-uzp.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll
M llvm/test/CodeGen/AArch64/illegal-float-ops.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
A llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.ll
A llvm/test/CodeGen/AArch64/machine-outliner-sort-per-priority.mir
M llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
M llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/vec-libcalls.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
A llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/ARM/arm-half-promote.ll
M llvm/test/CodeGen/ARM/build-attributes.ll
M llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll
M llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
M llvm/test/CodeGen/ARM/frame-chain.ll
M llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll
M llvm/test/CodeGen/ARM/machine-outliner-calls.mir
M llvm/test/CodeGen/ARM/machine-outliner-default.mir
M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
M llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
M llvm/test/CodeGen/ARM/misched-fp-basic.ll
M llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
M llvm/test/CodeGen/ARM/misched-int-basic.mir
M llvm/test/CodeGen/ARM/neon_vabd.ll
M llvm/test/CodeGen/ARM/proc-resource-sched.ll
M llvm/test/CodeGen/ARM/single-issue-r52.mir
M llvm/test/CodeGen/ARM/useaa.ll
M llvm/test/CodeGen/ARM/vaba.ll
M llvm/test/CodeGen/ARM/vabd.ll
M llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
M llvm/test/CodeGen/PowerPC/frameaddr.ll
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv32-libcall.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fptoi-rv64-libcall.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/select-fp.ll
A llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
A llvm/test/CodeGen/RISCV/xcvmem.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll
M llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll
A llvm/test/CodeGen/SPIRV/pointers/duplicate-type-ptr-def.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-global-dup.ll
A llvm/test/CodeGen/SPIRV/pointers/type-deduce-simple-for.ll
A llvm/test/CodeGen/SPIRV/transcoding/bitcast-diff-addrspace.ll
M llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll
M llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll
M llvm/test/CodeGen/Thumb/frame-access.ll
M llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
M llvm/test/CodeGen/Thumb/frame-chain.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/pr38539.ll
A llvm/test/CodeGen/X86/select-phi-s16-fp.ll
A llvm/test/DebugInfo/X86/DW_OP_LLVM_extract_bits.ll
A llvm/test/DebugInfo/dwarfdump-loclist-basetyperef.test
M llvm/test/MC/ARM/dfb-neg.s
M llvm/test/MC/ARM/dfb.s
A llvm/test/MC/ARM/invalid-armv8r.s
M llvm/test/MC/ARM/thumb-hints.s
M llvm/test/MC/Disassembler/ARM/dfb-thumb.txt
M llvm/test/MC/RISCV/insn.s
M llvm/test/MC/RISCV/insn_c.s
M llvm/test/Transforms/InstCombine/icmp-equality-xor.ll
M llvm/test/Transforms/InstCombine/icmp-or.ll
M llvm/test/Transforms/InstCombine/pow-1.ll
M llvm/test/Transforms/InstCombine/prevent-cmp-merge.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-calls-libsystem-darwin.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LoopVectorize/dead_instructions.ll
M llvm/test/Transforms/Reassociate/shifttest.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-discriminator.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-verify.ll
M llvm/test/Transforms/SimplifyCFG/ARM/switch-to-lookup-table.ll
M llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv32.ll
M llvm/test/Transforms/SimplifyCFG/RISCV/switch_to_lookup_table-rv64.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
M llvm/tools/llvm-jitlink/CMakeLists.txt
M llvm/unittests/IR/DemandedBitsTest.cpp
M llvm/unittests/ProfileData/MemProfTest.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
M llvm/unittests/Support/KnownBitsTest.h
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn
M llvm/utils/gn/secondary/clang/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-config/BUILD.gn
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.h
M mlir/lib/Target/LLVMIR/DebugTranslation.cpp
M mlir/lib/Target/LLVMIR/DebugTranslation.h
M mlir/test/CAPI/llvm.c
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
M mlir/test/Dialect/Linalg/reshape_fusion.mlir
M mlir/test/Dialect/Linalg/transform-lower-pack.mlir
M mlir/test/Dialect/SCF/transform-ops.mlir
M mlir/test/Dialect/Tensor/canonicalize.mlir
A mlir/test/Dialect/Vector/vector-deinterleave-lowering-transforms.mlir
M mlir/test/Dialect/Vector/vector-transfer-flatten.mlir
R mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/lit.local.cfg
R mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/test-setArmSVLBits.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-setArmSVLBits.mlir
R mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/lit.local.cfg
R mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-scalable-deinterleave.mlir
R mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/Emulated/test-setArmVLBits.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-scalable-deinterleave.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-setArmVLBits.mlir
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/lit.cfg.py
M mlir/test/python/ir/affine_expr.py
M mlir/test/python/ir/attributes.py
M mlir/test/python/ir/builtin_types.py
M offload/CMakeLists.txt
M openmp/CMakeLists.txt
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
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