[all-commits] [llvm/llvm-project] 5e0fc9: [clang-format] Fix a bug in `AlignAfterOpenBracket...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Fri Jun 7 10:23:50 PDT 2024
Branch: refs/heads/users/MaskRay/spr/elf-implement-force-group-allocation
Home: https://github.com/llvm/llvm-project
Commit: 5e0fc93d01c216544c12b60c30fe8ac6c9931eb9
https://github.com/llvm/llvm-project/commit/5e0fc93d01c216544c12b60c30fe8ac6c9931eb9
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Fix a bug in `AlignAfterOpenBracket: DontAlign` (#94561)
Fixes #94555.
Commit: 79cd6c3d01c6c69ca870418a3c602dbd1bef29e4
https://github.com/llvm/llvm-project/commit/79cd6c3d01c6c69ca870418a3c602dbd1bef29e4
Author: Thurston Dang <thurston at google.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
A compiler-rt/test/dfsan/sscanf.c
Log Message:
-----------
[dfsan] Add test case for sscanf (#94700)
This test case shows a limitation of DFSan's sscanf implementation
(introduced in https://reviews.llvm.org/D153775): it simply ignores
ordinary characters in the format string, instead of actually comparing
them against the input. This may change the semantics of instrumented
programs.
Importantly, this also means that DFSan's release_shadow_space.c test,
which relies on sscanf to scrape the RSS from /proc/maps output, will
incorrectly match lines that don't contain RSS information. As a result,
it adding together numbers from irrelevant output (e.g., base
addresses), resulting in test flakiness
(https://github.com/llvm/llvm-project/issues/91287).
Commit: a1fa43d030168d1ecd04031b4790b101e651770a
https://github.com/llvm/llvm-project/commit/a1fa43d030168d1ecd04031b4790b101e651770a
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M lld/ELF/Writer.cpp
Log Message:
-----------
[ELF] Simplify code. NFC
Make it easier to add CREL support.
Commit: f42025c2178b30894df657af6aa92e45c7cc0dbc
https://github.com/llvm/llvm-project/commit/f42025c2178b30894df657af6aa92e45c7cc0dbc
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
Log Message:
-----------
[SPIRV] Fix -Wunused-but-set-variable. NFC
Commit: 59003d714a9447bf03e0ce25ad4492290e80b110
https://github.com/llvm/llvm-project/commit/59003d714a9447bf03e0ce25ad4492290e80b110
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Add tests for expanding `foldSelectValueEquivalence`; NFC
Commit: 7e7c29ba087e38056b91f1d783db0883dcc33ef7
https://github.com/llvm/llvm-project/commit/7e7c29ba087e38056b91f1d783db0883dcc33ef7
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/abs-1.ll
M llvm/test/Transforms/InstCombine/select.ll
Log Message:
-----------
[InstCombine] Improve coverage of `foldSelectValueEquivalence` for constants
We don't need the `noundef` check if the new simplification is a
constant.
This cleans up regressions from folding multiuse:
`(icmp eq/ne (sub/xor x, y), 0)` -> `(icmp eq/ne x, y)`.
Closes #88298
Commit: 2d65097b4ff18f99e4baf18e2e0b155ecf478b0a
https://github.com/llvm/llvm-project/commit/2d65097b4ff18f99e4baf18e2e0b155ecf478b0a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
Log Message:
-----------
[RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (#94660)
Instead of having multiple places insert into the Features vector
independently, check all the conditions in one place.
This avoids a subtle ordering requirement that -mstrict-align processing
had to be done after the others.
Commit: c967c7e0223845b54a5220e2d4211fee50c5fb30
https://github.com/llvm/llvm-project/commit/c967c7e0223845b54a5220e2d4211fee50c5fb30
Author: Nour <nourr313 at proton.me>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
[clang-format][NFC] Remove an else after a return statement (#94548)
Commit: a10135f4922624f92c3a108d23ab64adc09dd285
https://github.com/llvm/llvm-project/commit/a10135f4922624f92c3a108d23ab64adc09dd285
Author: Gedare Bloom <gedare at rtems.org>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format]: Annotate colons found in inline assembly (#92617)
Short-circuit the parsing of tok::colon to label colons found within
lines starting with asm as InlineASMColon.
Fixes #92616.
---------
Co-authored-by: Owen Pan <owenpiano at gmail.com>
Commit: f2441b0297501610b59527f93e3174c814d63941
https://github.com/llvm/llvm-project/commit/f2441b0297501610b59527f93e3174c814d63941
Author: Weining Lu <luweining at loongson.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
R clang/test/Driver/loongarch-default-features.c
A clang/test/Driver/loongarch-features.c
Log Message:
-----------
[Driver][test] Rename loongarch-{default-,}features.c
Commit: 5c104879c1a98eeb845c03e7c45206bd48e88f0c
https://github.com/llvm/llvm-project/commit/5c104879c1a98eeb845c03e7c45206bd48e88f0c
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/AST/ASTUnresolvedSet.h
M clang/include/clang/AST/DeclAccessPair.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclID.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/Serialization/ModuleManager.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ModuleFile.cpp
A clang/test/Modules/no-transitive-decls-change.cppm
Log Message:
-----------
[serialization] no transitive decl change (#92083)
Following of https://github.com/llvm/llvm-project/pull/86912
The motivation of the patch series is that, for a module interface unit
`X`, when the dependent modules of `X` changes, if the changes is not
relevant with `X`, we hope the BMI of `X` won't change. For the specific
patch, we hope if the changes was about irrelevant declaration changes,
we hope the BMI of `X` won't change. **However**, I found the patch
itself is not very useful in practice, since the adding or removing
declarations, will change the state of identifiers and types in most
cases.
That said, for the most simple example,
```
// partA.cppm
export module m:partA;
// partA.v1.cppm
export module m:partA;
export void a() {}
// partB.cppm
export module m:partB;
export void b() {}
// m.cppm
export module m;
export import :partA;
export import :partB;
// onlyUseB;
export module onlyUseB;
import m;
export inline void onluUseB() {
b();
}
```
the BMI of `onlyUseB` will change after we change the implementation of
`partA.cppm` to `partA.v1.cppm`. Since `partA.v1.cppm` introduces new
identifiers and types (the function prototype).
So in this patch, we have to write the tests as:
```
// partA.cppm
export module m:partA;
export int getA() { ... }
export int getA2(int) { ... }
// partA.v1.cppm
export module m:partA;
export int getA() { ... }
export int getA(int) { ... }
export int getA2(int) { ... }
// partB.cppm
export module m:partB;
export void b() {}
// m.cppm
export module m;
export import :partA;
export import :partB;
// onlyUseB;
export module onlyUseB;
import m;
export inline void onluUseB() {
b();
}
```
so that the new introduced declaration `int getA(int)` doesn't introduce
new identifiers and types, then the BMI of `onlyUseB` can keep
unchanged.
While it looks not so great, the patch should be the base of the patch
to erase the transitive change for identifiers and types since I don't
know how can we introduce new types and identifiers without introducing
new declarations. Given how tightly the relationship between
declarations, types and identifiers, I think we can only reach the ideal
state after we made the series for all of the three entties.
The design of the patch is similar to
https://github.com/llvm/llvm-project/pull/86912, which extends the
32-bit DeclID to 64-bit and use the higher bits to store the module file
index and the lower bits to store the Local Decl ID.
A slight difference is that we only use 48 bits to store the new DeclID
since we try to use the higher 16 bits to store the module ID in the
prefix of Decl class. Previously, we use 32 bits to store the module ID
and 32 bits to store the DeclID. I don't want to allocate additional
space so I tried to make the additional space the same as 64 bits. An
potential interesting thing here is about the relationship between the
module ID and the module file index. I feel we can get the module file
index by the module ID. But I didn't prove it or implement it. Since I
want to make the patch itself as small as possible. We can make it in
the future if we want.
Another change in the patch is the new concept Decl Index, which means
the index of the very big array `DeclsLoaded` in ASTReader. Previously,
the index of a loaded declaration is simply the Decl ID minus
PREDEFINED_DECL_NUMs. So there are some places they got used
ambiguously. But this patch tried to split these two concepts.
As https://github.com/llvm/llvm-project/pull/86912 did, the change will
increase the on-disk PCM file sizes. As the declaration ID may be the
most IDs in the PCM file, this can have the biggest impact on the size.
In my experiments, this change will bring 6.6% increase of the on-disk
PCM size. No compile-time performance regression observed. Given the
benefits in the motivation example, I think the cost is worthwhile.
Commit: 222e0a042c1c7c3b1aec7557bcb60d1543c1737a
https://github.com/llvm/llvm-project/commit/222e0a042c1c7c3b1aec7557bcb60d1543c1737a
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ScheduleDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
Log Message:
-----------
[llvm][ScheduleDAG] Re-arrange SUnit's members to make it smaller (#94547)
before:
```
*** Dumping AST Record Layout
0 | class llvm::SUnit
0 | SDNode * Node
8 | MachineInstr * Instr
16 | SUnit * OrigNode
24 | const MCSchedClassDesc * SchedClass
32 | class llvm::SmallVector<class llvm::SDep, 4> Preds
32 | class llvm::SmallVectorImpl<class llvm::SDep> (base)
32 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
32 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
32 | class llvm::SmallVectorBase<uint32_t> (base)
32 | void * BeginX
40 | unsigned int Size
44 | unsigned int Capacity
48 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
48 | char[64] InlineElts
112 | class llvm::SmallVector<class llvm::SDep, 4> Succs
112 | class llvm::SmallVectorImpl<class llvm::SDep> (base)
112 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
112 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
112 | class llvm::SmallVectorBase<uint32_t> (base)
112 | void * BeginX
120 | unsigned int Size
124 | unsigned int Capacity
128 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
128 | char[64] InlineElts
192 | unsigned int NodeNum
196 | unsigned int NodeQueueId
200 | unsigned int NumPreds
204 | unsigned int NumSuccs
208 | unsigned int NumPredsLeft
212 | unsigned int NumSuccsLeft
216 | unsigned int WeakPredsLeft
220 | unsigned int WeakSuccsLeft
224 | unsigned short NumRegDefsLeft
226 | unsigned short Latency
228:0-0 | _Bool isVRegCycle
228:1-1 | _Bool isCall
228:2-2 | _Bool isCallOp
228:3-3 | _Bool isTwoAddress
228:4-4 | _Bool isCommutable
228:5-5 | _Bool hasPhysRegUses
228:6-6 | _Bool hasPhysRegDefs
228:7-7 | _Bool hasPhysRegClobbers
229:0-0 | _Bool isPending
229:1-1 | _Bool isAvailable
229:2-2 | _Bool isScheduled
229:3-3 | _Bool isScheduleHigh
229:4-4 | _Bool isScheduleLow
229:5-5 | _Bool isCloned
229:6-6 | _Bool isUnbuffered
229:7-7 | _Bool hasReservedResource
232 | Sched::Preference SchedulingPref
236:0-0 | _Bool isDepthCurrent
236:1-1 | _Bool isHeightCurrent
240 | unsigned int Depth
244 | unsigned int Height
248 | unsigned int TopReadyCycle
252 | unsigned int BotReadyCycle
256 | const TargetRegisterClass * CopyDstRC
264 | const TargetRegisterClass * CopySrcRC
| [sizeof=272, dsize=272, align=8,
| nvsize=272, nvalign=8]
```
after:
```
*** Dumping AST Record Layout
0 | class llvm::SUnit
0 | union llvm::SUnit::(anonymous at /Users/jonathan_roelofs/llvm-upstream/llvm/include/llvm/CodeGen/ScheduleDAG.h:246:5)
0 | SDNode * Node
0 | MachineInstr * Instr
8 | SUnit * OrigNode
16 | const MCSchedClassDesc * SchedClass
24 | const TargetRegisterClass * CopyDstRC
32 | const TargetRegisterClass * CopySrcRC
40 | class llvm::SmallVector<class llvm::SDep, 4> Preds
40 | class llvm::SmallVectorImpl<class llvm::SDep> (base)
40 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
40 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
40 | class llvm::SmallVectorBase<uint32_t> (base)
40 | void * BeginX
48 | unsigned int Size
52 | unsigned int Capacity
56 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
56 | char[64] InlineElts
120 | class llvm::SmallVector<class llvm::SDep, 4> Succs
120 | class llvm::SmallVectorImpl<class llvm::SDep> (base)
120 | class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
120 | class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
120 | class llvm::SmallVectorBase<uint32_t> (base)
120 | void * BeginX
128 | unsigned int Size
132 | unsigned int Capacity
136 | struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
136 | char[64] InlineElts
200 | unsigned int NodeNum
204 | unsigned int NodeQueueId
208 | unsigned int NumPreds
212 | unsigned int NumSuccs
216 | unsigned int NumPredsLeft
220 | unsigned int NumSuccsLeft
224 | unsigned int WeakPredsLeft
228 | unsigned int WeakSuccsLeft
232 | unsigned int TopReadyCycle
236 | unsigned int BotReadyCycle
240 | unsigned int Depth
244 | unsigned int Height
248:0-0 | _Bool isVRegCycle
248:1-1 | _Bool isCall
248:2-2 | _Bool isCallOp
248:3-3 | _Bool isTwoAddress
248:4-4 | _Bool isCommutable
248:5-5 | _Bool hasPhysRegUses
248:6-6 | _Bool hasPhysRegDefs
248:7-7 | _Bool hasPhysRegClobbers
249:0-0 | _Bool isPending
249:1-1 | _Bool isAvailable
249:2-2 | _Bool isScheduled
249:3-3 | _Bool isScheduleHigh
249:4-4 | _Bool isScheduleLow
249:5-5 | _Bool isCloned
249:6-6 | _Bool isUnbuffered
249:7-7 | _Bool hasReservedResource
250 | unsigned short NumRegDefsLeft
252 | unsigned short Latency
254:0-0 | _Bool isDepthCurrent
254:1-1 | _Bool isHeightCurrent
254:2-2 | _Bool isNode
254:3-3 | _Bool isInst
254:4-7 | Sched::Preference SchedulingPref
| [sizeof=256, dsize=255, align=8,
| nvsize=255, nvalign=8]
```
Commit: 4f70c5ec4a57e84642fa0772536f120cd9c75edb
https://github.com/llvm/llvm-project/commit/4f70c5ec4a57e84642fa0772536f120cd9c75edb
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/AST/ASTUnresolvedSet.h
M clang/include/clang/AST/DeclAccessPair.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclID.h
M clang/include/clang/AST/UnresolvedSet.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/include/clang/Serialization/ASTReader.h
M clang/include/clang/Serialization/ModuleFile.h
M clang/include/clang/Serialization/ModuleManager.h
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ModuleFile.cpp
R clang/test/Modules/no-transitive-decls-change.cppm
Log Message:
-----------
Revert "[serialization] no transitive decl change (#92083)"
This reverts commit 5c104879c1a98eeb845c03e7c45206bd48e88f0c.
The ArmV7 bot is complaining the change breaks the alignment.
Commit: 0e1d6e2fc48accbfdbb349dc460a4e91edf1d884
https://github.com/llvm/llvm-project/commit/0e1d6e2fc48accbfdbb349dc460a4e91edf1d884
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/build_vector-r600.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
Log Message:
-----------
[AMDGPU] Auto-generating lit test patterns (NFC) (#93837)
Test CodeGen/AMDGPU/build_vector.ll has the lit patterns partially
hand-written and the rest auto-generated. It doesn't look good when
changes are required with future patches. Auto-generating the entire
pattern. Moved out the R600 test into build_vector-r600.ll.
Commit: e96e7f1f33637ba5080c82e874622948c0a0c25b
https://github.com/llvm/llvm-project/commit/e96e7f1f33637ba5080c82e874622948c0a0c25b
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
A llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
A llvm/test/CodeGen/AMDGPU/xor-r600.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
Log Message:
-----------
[AMDGPU] Auto-generated some lit test patterns (NFC). (#94310)
Also, converted the R600 RUN lines from some tests into standalone tests.
Commit: 1bc8b3258e6d42f702fb11eb60d84d0e23935e3e
https://github.com/llvm/llvm-project/commit/1bc8b3258e6d42f702fb11eb60d84d0e23935e3e
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePassManager.h
A llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/PassBuilder.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
M llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
M llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill192.mir
M llvm/test/CodeGen/AMDGPU/spill224.mir
M llvm/test/CodeGen/AMDGPU/spill288.mir
M llvm/test/CodeGen/AMDGPU/spill320.mir
M llvm/test/CodeGen/AMDGPU/spill352.mir
M llvm/test/CodeGen/AMDGPU/spill384.mir
M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
M llvm/test/CodeGen/ARM/regalloc-fast-rewrite-implicits.mir
M llvm/test/CodeGen/MIR/Generic/runPass.mir
M llvm/test/CodeGen/PowerPC/spill-nor0.mir
M llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
M llvm/test/CodeGen/X86/bug47278-eflags-error.mir
M llvm/test/CodeGen/X86/bug47278.mir
M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
M llvm/test/CodeGen/X86/fastregalloc-selfloop.mir
M llvm/test/CodeGen/X86/fastregalloc-tied-undef.mir
M llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
M llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
M llvm/test/CodeGen/X86/virtreg-physreg-def-regallocfast.mir
A llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
Log Message:
-----------
[NewPM][CodeGen] Port `regallocfast` to new pass manager (#94426)
This pull request port `regallocfast` to new pass manager. It exposes
the parameter `filter` to handle different register classes for AMDGPU.
IIUC AMDGPU need to allocate different register classes separately so it
need implement its own `--<reg-class>-regalloc`. Now users can use e.g.
`-passe=regallocfast<filter=sgpr>` to allocate specific register class.
The command line option `--regalloc-npm` is still in work progress, plan
to reuse the syntax of passes, e.g. use
`--regalloc-npm=regallocfast<filter=sgpr>,greedy<filter=vgpr>` to
replace `--sgpr-regalloc` and `--vgpr-regalloc`.
Commit: 566befca28f5df9490ad4fcce31042d92526ba1e
https://github.com/llvm/llvm-project/commit/566befca28f5df9490ad4fcce31042d92526ba1e
Author: WANG Rui <wangrui at loongson.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
A llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
Log Message:
-----------
[NFC][LoongArch] Pre-commit tests for hoisting of PseudoLA*
Commit: a6350d63af63fb11d87d508965559bbb2833927d
https://github.com/llvm/llvm-project/commit/a6350d63af63fb11d87d508965559bbb2833927d
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
Log Message:
-----------
[test] Don't generate `regalloc-amdgpu.s` in #94426 (#94722)
The test will generate an empty `regalloc-amdgpu.s` file in test, which
causes an unresolved test.
Commit: c5ff983fe4a3180e13c7244a6ce9f5994b4379b4
https://github.com/llvm/llvm-project/commit/c5ff983fe4a3180e13c7244a6ce9f5994b4379b4
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/HeaderIncludeCycleCheck.cpp
Log Message:
-----------
[clang-tidy] refactor misc-header-include-cycle (#94697)
1. merge valid check
2. use range base loop
Commit: d231b50dba6cf1b3ab095d381ae622e9498bbb3c
https://github.com/llvm/llvm-project/commit/d231b50dba6cf1b3ab095d381ae622e9498bbb3c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M libcxx/.clang-tidy
M libcxx/include/__functional/bind.h
M libcxx/include/__mdspan/extents.h
Log Message:
-----------
[libc++] Fix naming of value template parameters (#76888)
Commit: 670fa2bd7a4d50c33bc24d4e3e1fa4079592b730
https://github.com/llvm/llvm-project/commit/670fa2bd7a4d50c33bc24d4e3e1fa4079592b730
Author: Gábor Horváth <xazax.hun at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/include/clang/Sema/Initialization.h
M clang/lib/Sema/SemaAvailability.cpp
A clang/test/Sema/attr-availability-macosx.cpp
Log Message:
-----------
Fix spurious non-strict availability warning (#94377)
The availability attributes are stored on the function declarations. The
code was looking for them in the function template declarations. This
resulted in spuriously diagnosing (non-strict) availablity issues in
contexts that are not available.
Co-authored-by: Gabor Horvath <gaborh at apple.com>
Commit: 1752740f4b4b752bbe2987a0de398c6f671ceb71
https://github.com/llvm/llvm-project/commit/1752740f4b4b752bbe2987a0de398c6f671ceb71
Author: Prashant Kumar <pk5561 at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir][tensor] Fix FoldTensorCastProducerOp for multiple result operations (#93374)
For patterns where there are multiple results apart from dpsInits, this
fails.
E.g.:
```
%13:2 = iree_codegen.ukernel.generic "iree_uk_unpack"
ins(%extracted_slice : tensor<?x1x16x16xf32>) outs(%11 :
tensor<?x?xf32>) ... -> tensor<?x?xf32>, i32
```
The above op has results apart from dpsInit and hence fails. The PR
assumes that the result has dpsInits followed by nonDpsInits.
Commit: ec94e7a93031549b1f4e21e560ff4d3db265973a
https://github.com/llvm/llvm-project/commit/ec94e7a93031549b1f4e21e560ff4d3db265973a
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M llvm/lib/MC/MCSection.cpp
Log Message:
-----------
[MC] MCSection::dump: print section name
Commit: 0b8acc06c42df9d444f669fff312fffffcacdfb9
https://github.com/llvm/llvm-project/commit/0b8acc06c42df9d444f669fff312fffffcacdfb9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/cxx20.cpp
Log Message:
-----------
[clang][Interp] Improve APValue machinery
Handle lvalues pointing to declarations, unions and member pointers.
Commit: d843c02aba5d253891ea0e599c4b6e25247c1af7
https://github.com/llvm/llvm-project/commit/d843c02aba5d253891ea0e599c4b6e25247c1af7
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/TargetParser/X86TargetParser.def
Log Message:
-----------
[X86] Assign AVX10_1 feature priority to align with gcc. (#94557)
gcc patch:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1f2ca510065a2033bac408eb5a960ef0126f25cc
Commit: 90b9922df2d8fb65a33eb9abd002fa9262863b5b
https://github.com/llvm/llvm-project/commit/90b9922df2d8fb65a33eb9abd002fa9262863b5b
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M lldb/include/lldb/Core/ValueObject.h
M lldb/include/lldb/Core/ValueObjectConstResult.h
M lldb/include/lldb/Core/ValueObjectConstResultCast.h
M lldb/include/lldb/Core/ValueObjectConstResultChild.h
M lldb/include/lldb/Core/ValueObjectConstResultImpl.h
M lldb/include/lldb/Core/ValueObjectRegister.h
M lldb/include/lldb/Core/ValueObjectVTable.h
M lldb/source/Core/ValueObject.cpp
M lldb/source/Core/ValueObjectConstResult.cpp
M lldb/source/Core/ValueObjectConstResultCast.cpp
M lldb/source/Core/ValueObjectConstResultChild.cpp
M lldb/source/Core/ValueObjectConstResultImpl.cpp
M lldb/source/Core/ValueObjectRegister.cpp
M lldb/source/Core/ValueObjectVTable.cpp
Log Message:
-----------
[lldb] Split ValueObject::CreateChildAtIndex into two functions (#94455)
The the function is doing two fairly different things, depending on how
it is called. While this allows for some code reuse, it also makes it
hard to override it correctly. Possibly for this reason
ValueObjectSynthetic overerides GetChildAtIndex instead, which forces it
to reimplement some of its functionality, most notably caching of
generated children.
Splitting this up makes it easier to move the caching to a common place
(and hopefully makes the code easier to follow in general).
Commit: c007883f0286a314eb69976ad14da2bce988fb55
https://github.com/llvm/llvm-project/commit/c007883f0286a314eb69976ad14da2bce988fb55
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/TargetParser/X86TargetParser.def
Log Message:
-----------
Revert "[X86] Assign AVX10_1 feature priority to align with gcc. (#94557)" (#94730)
This reverts commit d843c02aba5d253891ea0e599c4b6e25247c1af7.
Commit: b7d976d4e520a7acba71e006e1518d147a862138
https://github.com/llvm/llvm-project/commit/b7d976d4e520a7acba71e006e1518d147a862138
Author: Kazu Hirata <kazu at google.com>
Date: 2024-06-06 (Thu, 06 Jun 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[memprof] Use std::move in ContextEdge::ContextEdge (NFC) (#94687)
Since the constructor of ContextEdge takes ContextIds by value, we
should move it to the corresponding member variable as suggested by
clang-tidy's performance-unnecessary-value-param.
While we are at it, this patch updates a couple of callers. To avoid
the ambiguity in the evaluation order among the constructor arguments,
I'm calling computeAllocType before calling the constructor.
Commit: 4a7b8003012985028bdf637be0a9c7a71dff65d9
https://github.com/llvm/llvm-project/commit/4a7b8003012985028bdf637be0a9c7a71dff65d9
Author: Lang Hames <lhames at gmail.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Log Message:
-----------
[ORC] Switch ExecutionSession::ErrorReporter to use unique_function.
This allows the ReportError functor to hold move-only types.
Commit: f21c2fae95f76300c4230f75b6e97445932f6bc6
https://github.com/llvm/llvm-project/commit/f21c2fae95f76300c4230f75b6e97445932f6bc6
Author: hev <wangrui at loongson.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
Log Message:
-----------
[LoongArch] Set isReMaterializable on LU{12,32,52}I.D/ADDI.D and {X}ORI instructions (#94552)
Commit: d224a034a20016272a3257f7081d02f90eb9cc78
https://github.com/llvm/llvm-project/commit/d224a034a20016272a3257f7081d02f90eb9cc78
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
Log Message:
-----------
[SCEV] Use insert_or_assign() (NFC)
Commit: 240512c43234f58b3924cd90fe0781445d97e98d
https://github.com/llvm/llvm-project/commit/240512c43234f58b3924cd90fe0781445d97e98d
Author: hev <wangrui at loongson.cn>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M llvm/lib/Target/LoongArch/CMakeLists.txt
M llvm/lib/Target/LoongArch/LoongArch.h
A llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/test/CodeGen/LoongArch/global-address.ll
M llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
M llvm/test/CodeGen/LoongArch/intrinsic.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/br.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
M llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll
M llvm/utils/gn/secondary/llvm/lib/Target/LoongArch/BUILD.gn
Log Message:
-----------
[LoongArch] Add a pass to rewrite rd to r0 for non-computational instrs whose return values are unused (#94590)
This patch adds a peephole pass `LoongArchDeadRegisterDefinitions`. It
rewrites `rd` to `r0` when `rd` is marked as dead. It may improve the
register allocation and reduce pipeline hazards on CPUs without register
renaming and OOO.
Commit: c178000c28ed1925d5bf3b438e41f1f62adc712d
https://github.com/llvm/llvm-project/commit/c178000c28ed1925d5bf3b438e41f1f62adc712d
Author: Fangrui Song <i at maskray.me>
Date: 2024-06-07 (Fri, 07 Jun 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/HeaderIncludeCycleCheck.cpp
M clang/include/clang/Sema/Initialization.h
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Sema/SemaAvailability.cpp
M clang/test/AST/Interp/cxx20.cpp
R clang/test/Driver/loongarch-default-features.c
A clang/test/Driver/loongarch-features.c
A clang/test/Sema/attr-availability-macosx.cpp
M clang/tools/clang-format/ClangFormat.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
A compiler-rt/test/dfsan/sscanf.c
M libcxx/.clang-tidy
M libcxx/include/__functional/bind.h
M libcxx/include/__mdspan/extents.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/docs/ReleaseNotes.rst
M lld/docs/ld.lld.1
M lld/test/ELF/comdat.s
M lld/test/ELF/relocatable-comdat.s
M lldb/include/lldb/Core/ValueObject.h
M lldb/include/lldb/Core/ValueObjectConstResult.h
M lldb/include/lldb/Core/ValueObjectConstResultCast.h
M lldb/include/lldb/Core/ValueObjectConstResultChild.h
M lldb/include/lldb/Core/ValueObjectConstResultImpl.h
M lldb/include/lldb/Core/ValueObjectRegister.h
M lldb/include/lldb/Core/ValueObjectVTable.h
M lldb/source/Core/ValueObject.cpp
M lldb/source/Core/ValueObjectConstResult.cpp
M lldb/source/Core/ValueObjectConstResultCast.cpp
M lldb/source/Core/ValueObjectConstResultChild.cpp
M lldb/source/Core/ValueObjectConstResultImpl.cpp
M lldb/source/Core/ValueObjectRegister.cpp
M lldb/source/Core/ValueObjectVTable.cpp
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
A llvm/include/llvm/CodeGen/RegAllocFast.h
M llvm/include/llvm/CodeGen/ScheduleDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Passes/PassBuilder.h
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/MC/MCSection.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/LoongArch/CMakeLists.txt
M llvm/lib/Target/LoongArch/LoongArch.h
A llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
A llvm/test/CodeGen/AMDGPU/build_vector-r600.ll
M llvm/test/CodeGen/AMDGPU/build_vector.ll
A llvm/test/CodeGen/AMDGPU/fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fabs.ll
M llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
M llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
A llvm/test/CodeGen/AMDGPU/fneg-fabs-r600.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
M llvm/test/CodeGen/AMDGPU/fneg.ll
M llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
M llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill192.mir
M llvm/test/CodeGen/AMDGPU/spill224.mir
M llvm/test/CodeGen/AMDGPU/spill288.mir
M llvm/test/CodeGen/AMDGPU/spill320.mir
M llvm/test/CodeGen/AMDGPU/spill352.mir
M llvm/test/CodeGen/AMDGPU/spill384.mir
M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
A llvm/test/CodeGen/AMDGPU/xor-r600.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/ARM/regalloc-fast-rewrite-implicits.mir
M llvm/test/CodeGen/LoongArch/global-address.ll
M llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
M llvm/test/CodeGen/LoongArch/intrinsic.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/br.ll
M llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
A llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll
M llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
M llvm/test/CodeGen/MIR/Generic/runPass.mir
M llvm/test/CodeGen/PowerPC/spill-nor0.mir
M llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
M llvm/test/CodeGen/Thumb/high-reg-clobber.mir
M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
M llvm/test/CodeGen/X86/bug47278-eflags-error.mir
M llvm/test/CodeGen/X86/bug47278.mir
M llvm/test/CodeGen/X86/callbr-asm-outputs-regallocfast.mir
M llvm/test/CodeGen/X86/fastregalloc-selfloop.mir
M llvm/test/CodeGen/X86/fastregalloc-tied-undef.mir
M llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir
M llvm/test/CodeGen/X86/statepoint-fastregalloc.mir
M llvm/test/CodeGen/X86/virtreg-physreg-def-regallocfast.mir
M llvm/test/Transforms/InstCombine/abs-1.ll
M llvm/test/Transforms/InstCombine/select.ll
A llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/LoongArch/BUILD.gn
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
remove --inhibit-group-allocation. improve test
Created using spr 1.3.5-bogner
Compare: https://github.com/llvm/llvm-project/compare/880b593466dd...c178000c28ed
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