[all-commits] [llvm/llvm-project] 2afea7: [RISCV] Codegen support for XCVmem extension (#76916)

[Liao Chunyu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2afea7296812b7e12c6ec683e6858bd4cbe8dd8d
      https://github.com/llvm/llvm-project/commit/2afea7296812b7e12c6ec683e6858bd4cbe8dd8d
  Author: Liao Chunyu <chunyu at iscas.ac.cn>
  Date:   2024-06-07 (Fri, 07 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    A llvm/test/CodeGen/RISCV/xcvmem.ll

  Log Message:
  -----------
  [RISCV] Codegen support for XCVmem extension (#76916)

All post-Increment load/store, register-register load/store

spec:

https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst

Contributors: @CharKeaney, @jeremybennett, @lewis-revill,
@NandniJamnadas, @PaoloS02, @serkm, @simonpcook, @xingmingjie, @realqhc



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