[all-commits] [llvm/llvm-project] e16f2f: [AArch64] Override isLSRCostLess, take number of i...

[Graham Hunter via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e16f2f5d2491fde19afb63d5cec83625d391be30
      https://github.com/llvm/llvm-project/commit/e16f2f5d2491fde19afb63d5cec83625d391be30
  Author: Graham Hunter <graham.hunter at arm.com>
  Date:   2024-06-06 (Thu, 06 Jun 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
    M llvm/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll
    M llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-reuse.ll

  Log Message:
  -----------
  [AArch64] Override isLSRCostLess, take number of instructions into account (#84189)

Adds an AArch64-specific version of isLSRCostLess, changing the relative
importance of the various terms from the formulae being evaluated.

This has been split out from my vscale-aware LSR work, see the RFC for
reference:
https://discourse.llvm.org/t/rfc-vscale-aware-loopstrengthreduce/77131



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