[all-commits] [llvm/llvm-project] a3d9ca: [RISCV] Make the vsll->vadd intrinsic pattern supp...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a3d9ca929712ea7c662bb36830cf349271137f2e
      https://github.com/llvm/llvm-project/commit/a3d9ca929712ea7c662bb36830cf349271137f2e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-06-05 (Wed, 05 Jun 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/vsll.ll

  Log Message:
  -----------
  [RISCV] Make the vsll->vadd intrinsic pattern support tail undisturbed intrinsics.

We convert a shift left by 1 to vadd. But we only did it for
tail agnostic or masked intrinsics. This extends it to tail undisturbed
unmasked intrinsics.



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