[all-commits] [llvm/llvm-project] 54b20c: [DAG] computeKnownBits - abds(x, y) will be zero i...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 54b20cbb95fec00ebc0cc83c8d7ca885294c1016
      https://github.com/llvm/llvm-project/commit/54b20cbb95fec00ebc0cc83c8d7ca885294c1016
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-06-05 (Wed, 05 Jun 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/neon-abd.ll

  Log Message:
  -----------
  [DAG] computeKnownBits - abds(x, y) will be zero in the upper bits if x and y are sign-extended (#94448)

As reported on #94442 - if x and y have more than one signbit, then the upper bits of its absolute value are guaranteed to be zero

Sibling PR to #94382

Alive2: https://alive2.llvm.org/ce/z/7_z2Vc

Fixes #94442



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