[all-commits] [llvm/llvm-project] e63552: [DAG] computeKnownBits - abs(x) will be zero in th...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e635520be888335dd59874038d33e60cca3a7143
      https://github.com/llvm/llvm-project/commit/e635520be888335dd59874038d33e60cca3a7143
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-06-05 (Wed, 05 Jun 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/combine-abs.ll

  Log Message:
  -----------
  [DAG] computeKnownBits - abs(x) will be zero in the upper bits if x is sign-extended (#94382)

As reported on https://github.com/llvm/llvm-project/issues/94344 - if x has more than one signbit, then the upper bits of its absolute value are guaranteed to be zero

Alive2: https://alive2.llvm.org/ce/z/a87fHU

Fixes #94344



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