[all-commits] [llvm/llvm-project] d3a904: [lldb][RISCV] Add RegisterContextPOSIXCore for RIS...
Alexey Merzlyakov via All-commits
all-commits at lists.llvm.org
Wed Jun 5 02:15:10 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: d3a9043ec2ee7ea278be4f3c86823512e44d01bf
https://github.com/llvm/llvm-project/commit/d3a9043ec2ee7ea278be4f3c86823512e44d01bf
Author: Alexey Merzlyakov <60094858+AlexeyMerzlyakov at users.noreply.github.com>
Date: 2024-06-05 (Wed, 05 Jun 2024)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
M lldb/source/Plugins/Process/elf-core/CMakeLists.txt
A lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
A lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
M lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
A lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
Log Message:
-----------
[lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (#93297)
The PR adds the support of CoreDump debugging for RISC-V 64. It
implements new `RegisterContextCorePOSIX_riscv64` class.
Also, the contribution fixes `GetRegisterCount()` ->
`GetRegisterSetCount()` misprint in
`RegisterContextPOSIX_riscv64::GetRegisterSetCount()` method, which
leaded to `set && "Register set should be valid."` assertion during
`register info aX` command call.
The patch was tested (on coredumps generated for simple Integer/FP
calculation code) for _cross x86_64 -> RISCV_ and _native RISCV_ LLDB
builds. There were performed basic LLDB functionality tests, such as:
- CoreDump file load
- Backtrace / frames
- GP/FP registers read/info/list
- Basic switch between threads
- Disassembler code
- Memory regions read / display
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