[all-commits] [llvm/llvm-project] d2cdc8: [NewPM][CodeGen] Port selection dag isel to new pa...

Sat Jun 1 18:12:54 PDT 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d2cdc8ab45d74f8691f73cb5a2b8c431585cd449
      https://github.com/llvm/llvm-project/commit/d2cdc8ab45d74f8691f73cb5a2b8c431585cd449
  Author: paperchalice <liujunchang97 at outlook.com>
  Date:   2024-06-02 (Sun, 02 Jun 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/include/llvm/CodeGen/SelectionDAGISel.h
    M llvm/include/llvm/CodeGen/StackProtector.h
    M llvm/include/llvm/Passes/CodeGenPassBuilder.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/lib/Target/AArch64/AArch64.h
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPassBuilder.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
    M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/ARC/ARC.h
    M llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
    M llvm/lib/Target/ARC/ARCTargetMachine.cpp
    M llvm/lib/Target/ARM/ARM.h
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/lib/Target/ARM/ARMTargetMachine.cpp
    M llvm/lib/Target/AVR/AVR.h
    M llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
    M llvm/lib/Target/AVR/AVRTargetMachine.cpp
    M llvm/lib/Target/BPF/BPF.h
    M llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
    M llvm/lib/Target/BPF/BPFTargetMachine.cpp
    M llvm/lib/Target/CSKY/CSKY.h
    M llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
    M llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
    M llvm/lib/Target/Hexagon/Hexagon.h
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
    M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
    M llvm/lib/Target/Lanai/Lanai.h
    M llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
    M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
    M llvm/lib/Target/LoongArch/LoongArch.h
    M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
    M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
    M llvm/lib/Target/M68k/M68k.h
    M llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
    M llvm/lib/Target/M68k/M68kTargetMachine.cpp
    M llvm/lib/Target/MSP430/MSP430.h
    M llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
    M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
    M llvm/lib/Target/Mips/Mips.h
    M llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
    M llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
    M llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
    M llvm/lib/Target/Mips/MipsISelDAGToDAG.h
    M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
    M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
    M llvm/lib/Target/Mips/MipsTargetMachine.cpp
    M llvm/lib/Target/NVPTX/NVPTX.h
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
    M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
    M llvm/lib/Target/PowerPC/PPC.h
    M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/lib/Target/Sparc/Sparc.h
    M llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
    M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
    M llvm/lib/Target/SystemZ/SystemZ.h
    M llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
    M llvm/lib/Target/VE/VE.h
    M llvm/lib/Target/VE/VEISelDAGToDAG.cpp
    M llvm/lib/Target/VE/VETargetMachine.cpp
    M llvm/lib/Target/WebAssembly/WebAssembly.h
    M llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
    M llvm/lib/Target/X86/X86.h
    M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    A llvm/lib/Target/X86/X86ISelDAGToDAG.h
    A llvm/lib/Target/X86/X86PassRegistry.def
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    M llvm/lib/Target/X86/X86TargetMachine.h
    M llvm/lib/Target/XCore/XCore.h
    M llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
    M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
    M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    M llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-ctlz-cttz.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-ctpop.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-min-max.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-not-isel.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
    M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f32.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs-divergence-driven-isel.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/global-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll
    M llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll
    M llvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/X86/apx/no-rex2-general.ll
    M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
    M llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
    M llvm/test/CodeGen/X86/apx/no-rex2-special.ll
    M llvm/test/tools/llc/new-pm/start-stop.ll

  Log Message:
  -----------
  [NewPM][CodeGen] Port selection dag isel to new pass manager (#83567)

Port selection dag isel to new pass manager.
Only `AMDGPU` and `X86` support new pass version. `-verify-machineinstrs` in new pass manager belongs to verify instrumentation, it is enabled by default.

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