[all-commits] [llvm/llvm-project] 6147a7: [RISCV] Adjust FP load latencies from 6 to 5 in Si...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6147a7b5f9479a4163c07064a9c78c2d5fe40d27
      https://github.com/llvm/llvm-project/commit/6147a7b5f9479a4163c07064a9c78c2d5fe40d27
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-05-30 (Thu, 30 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
    A llvm/test/tools/llvm-mca/RISCV/SiFiveP600/load.s

  Log Message:
  -----------
  [RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)

According to our performance measurements, FLH/W/D have load latencies
closer to 5 rather than 6 in these two models.



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