[all-commits] [llvm/llvm-project] 3fee8b: [GISel] LegalizationArtifactCombiner: Elide redund...
Sergei Barannikov via All-commits
all-commits at lists.llvm.org
Thu May 30 02:41:04 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 3fee8b346928a24975ebbd6984b583c01ec82955
https://github.com/llvm/llvm-project/commit/3fee8b346928a24975ebbd6984b583c01ec82955
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2024-05-30 (Thu, 30 May 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
M llvm/test/CodeGen/RISCV/GlobalISel/jumptable.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-jump-table-brjt-rv64.mir
Log Message:
-----------
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
This is similar to 373c343a, but for targets with zero-or-negative-one
booleans.
The difference in tests is mostly due to G_SEXT_INREG being illegal for
some targets, in which case it gets expanded into G_SHL/G_ASHR pair,
which is not currently optimized by the combiner.
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