[all-commits] [llvm/llvm-project] 23366d: [AArch64][GlobalISel] Combine MUL(AND(LSHR(X, 15)...

[chuongg3 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 23366d4153e1e521a7e5b88d42afea69fb888be7
      https://github.com/llvm/llvm-project/commit/23366d4153e1e521a7e5b88d42afea69fb888be7
  Author: chuongg3 <chuong.goh at arm.com>
  Date:   2024-05-29 (Wed, 29 May 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/test/CodeGen/AArch64/mulcmle.ll

  Log Message:
  -----------
   [AArch64][GlobalISel] Combine MUL(AND(LSHR(X, 15), 0x10001), 0xffff) to CMLTz (#92915)

This patch mirrors the following SelectionDAG patch for GlobalISel:
https://reviews.llvm.org/D130874



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