[all-commits] [llvm/llvm-project] 4e0bd3: [MachineLICM] Hoist copies of constant physical re...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e0bd3fab4b6a54342c9bed14f205895da3cf0d9
      https://github.com/llvm/llvm-project/commit/4e0bd3fab4b6a54342c9bed14f205895da3cf0d9
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-05-29 (Wed, 29 May 2024)

  Changed paths:
    M llvm/lib/CodeGen/MachineLICM.cpp
    M llvm/test/CodeGen/AArch64/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
    M llvm/test/CodeGen/AArch64/machine-sink-cache-invalidation.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AVR/shift.ll
    A llvm/test/CodeGen/RISCV/machinelicm-constant-phys-reg.ll
    M llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
    M llvm/test/CodeGen/RISCV/vlenb.ll

  Log Message:
  -----------
  [MachineLICM] Hoist copies of constant physical register (#93285)

Previously, we just check if the source is a virtual register and
this prevents some potential hoists.

We can see some improvements in AArch64/RISCV tests.



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