[all-commits] [llvm/llvm-project] f7c8a0: [RISCV] Combine vXi32 (mul (and (lshr X, 15), 0x10...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7c8a0339c64810a3c1b28d9b3b20e02a2be6232
      https://github.com/llvm/llvm-project/commit/f7c8a0339c64810a3c1b28d9b3b20e02a2be6232
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-05-28 (Tue, 28 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/mul-combine.ll

  Log Message:
  -----------
  [RISCV] Combine vXi32 (mul (and (lshr X, 15), 0x10001), 0xffff) -> (bitcast (sra (v2Xi16 (bitcast X)), 15)) (#93565)

Similar for i16 and i64 elements for both fixed and scalable vectors.

This reduces the number of vector instructions, but increases vl/vtype
toggles.

This reduces some code in 525.x264_r from SPEC2017. In that usage, the
vectors are fixed with a small number of elements so vsetivli can be
used.

This is similar to `performMulVectorCmpZeroCombine` from AArch64.



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