[all-commits] [llvm/llvm-project] 64ed69: Reland "[SimplifyCFG] When only one case value is ...

[Qiongsi Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 64ed699b3d811407e5a9f1111f63e11dc7f7dd80
      https://github.com/llvm/llvm-project/commit/64ed699b3d811407e5a9f1111f63e11dc7f7dd80
  Author: DianQK <dianqk at dianqk.net>
  Date:   2024-05-25 (Sat, 25 May 2024)

  Changed paths:
    M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
    A llvm/test/Transforms/SimplifyCFG/switch-dead-default-lookup-table.ll
    M llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll

  Log Message:
  -----------
  Reland "[SimplifyCFG] When only one case value is missing, replace default with that case (#76669)"

When the default branch is the last case, we can transform that branch
into a concrete branch with an unreachable default branch.

```llvm
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define i64 @src(i64 %0) {
  %2 = urem i64 %0, 4
  switch i64 %2, label %5 [
    i64 1, label %3
    i64 2, label %3
    i64 3, label %4
  ]

3:                                                ; preds = %1, %1
  br label %5

4:                                                ; preds = %1
  br label %5

5:                                                ; preds = %1, %4, %3
  %.0 = phi i64 [ 2, %4 ], [ 1, %3 ], [ 0, %1 ]
  ret i64 %.0
}

define i64 @tgt(i64 %0) {
  %2 = urem i64 %0, 4
  switch i64 %2, label %unreachable [
    i64 0, label %5
    i64 1, label %3
    i64 2, label %3
    i64 3, label %4
  ]

unreachable:                              ; preds = %1
  unreachable

3:                                                ; preds = %1, %1
  br label %5

4:                                                ; preds = %1
  br label %5

5:                                                ; preds = %1, %4, %3
  %.0 = phi i64 [ 2, %4 ], [ 1, %3 ], [ 0, %1 ]
  ret i64 %.0
}
```

Alive2: https://alive2.llvm.org/ce/z/Y-PGXv

After transform to a lookup table, I believe `tgt` is better code.

The final instructions are as follows:

```asm
src:                                    # @src
        and     edi, 3
        lea     rax, [rdi - 1]
        cmp     rax, 2
        ja      .LBB0_1
        mov     rax, qword ptr [8*rdi + .Lswitch.table.src-8]
        ret
.LBB0_1:
        xor     eax, eax
        ret
tgt:                                    # @tgt
        and     edi, 3
        mov     rax, qword ptr [8*rdi + .Lswitch.table.tgt]
        ret
.Lswitch.table.src:
        .quad   1                               # 0x1
        .quad   1                               # 0x1
        .quad   2                               # 0x2

.Lswitch.table.tgt:
        .quad   0                               # 0x0
        .quad   1                               # 0x1
        .quad   1                               # 0x1
        .quad   2                               # 0x2
```

Godbolt: https://llvm.godbolt.org/z/borME8znd

Closes #73446.

(cherry picked from commit 7d81e072712f4e6a150561b5538ccebda289aa13)


  Commit: 7dc2f6602212bf0a0433c157b70e4fc0d70bb730
      https://github.com/llvm/llvm-project/commit/7dc2f6602212bf0a0433c157b70e4fc0d70bb730
  Author: Qiongsi Wu <274595+qiongsiwu at users.noreply.github.com>
  Date:   2024-05-25 (Sat, 25 May 2024)

  Changed paths:
    M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
    M llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll

  Log Message:
  -----------
  Reland "[SimplifyCFG] `switch`: Do Not Transform the Default Case if the Condition is Too Wide (#77831)"

https://github.com/llvm/llvm-project/pull/76669 taught SimplifyCFG to
handle switches when `default` has only one case. When the `switch`'s
condition is wider than 64 bit, the current implementation can calculate
the wrong default value. This PR skips cases where the condition is too
wide.

(cherry picked from commit 39bb790b906f4921a5d9fc09e856abe53ae7a320)


Compare: https://github.com/llvm/llvm-project/compare/1c90de5fe3d9...7dc2f6602212

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