[all-commits] [llvm/llvm-project] 9a038f: [RISCV] PseudoMovImm is not a IsSignExtendingOpW i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a038fceb3fae8e77c0118633866c04d6de4407b
      https://github.com/llvm/llvm-project/commit/9a038fceb3fae8e77c0118633866c04d6de4407b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-05-24 (Fri, 24 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISCV] PseudoMovImm is not a IsSignExtendingOpW instruction.

We only know it expands to a 2 instruction sequence, not necessarily
a sign extended sequence.

Happened to notice while I was looking at naming for the proposed
rematerializable LUI+ADDI for addresses.



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