[all-commits] [llvm/llvm-project] 66b5f1: [RISCV] Do not check PostRAScheduler in enablePost...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 66b5f16b2fc2ec9e34189c4042f0bea57291d2a4
      https://github.com/llvm/llvm-project/commit/66b5f16b2fc2ec9e34189c4042f0bea57291d2a4
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-05-24 (Fri, 24 May 2024)

  Changed paths:
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h

  Log Message:
  -----------
  [RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781)

On RISC-V, there are a few ways to control whether the
PostMachineScheduler is enabled. If `-enable-post-misched` is passed or
passed with a value of true, then the PostMachineScheduler is enabled.
If it is passed with a value of false then the PostMachineScheduler is
disabled. If the option is not passed at all, then
`RISCVSubtarget::enablePostRAMachineScheduler` decides whether the pass
should be enabled or not. `TargetSubtargetInfo::enablePostRAScheduler`
and `TargetSubtargetInfo::enablePostRAMachineScheduler` who check the
SchedModel value are not called by RISC-V backend.

`RISCVSubtarget::enablePostRAMachineScheduler` currently checks if the
active scheduler model sets `PostRAScheduler`. If it is set to true by
the scheduler model, then the pass is enabled. If it is not set to true
by the scheduler model, then the value of `UsePostRAScheduler` subtarget
feature is used.

I argue that the RISC-V backend should not use `PostRAScheduler` field
of the scheduler model to control whether the PostMachineScheduler is
enabled for the following reasons:

1. No other targets use this value to control whether
PostMachineScheduler is enabled. They only use it to check whether the
legacy PostRASchedulerList scheduler is enabled.

2. We can add the `UsePostRAScheduler` feature to the processor
definition in RISCVProcessors.td to tie a processor to whether the pass
should be enabled by default. This makes the feature and the sched model
field redundant.

3. Since these options are redundant, we should prefer the feature,
since we can set `+` and `-` on the feature, but the value of the
scheduler cannot be controlled on the command line.

4. Keeping both options allows us to set the feature and the scheduler
model value to conflicting values. Although the scheduler model value
will win out, it feels awkward to allow it.



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