[all-commits] [llvm/llvm-project] a1c9b9: [SelectionDAG][RISCV][VE] Rename VP_ASHR->VP_SRA V...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a1c9b9673c7408c64ac0d809e4aec5aee2eb2eb8
      https://github.com/llvm/llvm-project/commit/a1c9b9673c7408c64ac0d809e4aec5aee2eb2eb8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-05-24 (Fri, 24 May 2024)

  Changed paths:
    M llvm/include/llvm/IR/VPIntrinsics.def
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/VE/VVPNodes.def

  Log Message:
  -----------
  [SelectionDAG][RISCV][VE] Rename VP_ASHR->VP_SRA VP_LSHR->VP_SRL. (#93221)

This maintains consistency with the non-VP ISD opcodes.



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