[all-commits] [llvm/llvm-project] 25b65b: [RISCV][LSR] Account for temporary register for ba...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 25b65be43df56c1b7bea3fe2596fb36c2788d7af
      https://github.com/llvm/llvm-project/commit/25b65be43df56c1b7bea3fe2596fb36c2788d7af
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-05-22 (Wed, 22 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll

  Log Message:
  -----------
  [RISCV][LSR] Account for temporary register for base addition (#92296)

An LSR formula may require the addition of multiple base or scale
registers, this sum reduction requires a temporary register to perform.
Since the formulas are independent, we only need one temporary,
regardless of the number of unique formula. Each formula can reuse the
same temporary. A later CSE pass may come along and combine
sub-expressions - but then the register pressure would be that passes
problem to consider.

This change fixes up the costing in the RISCV specific way, but this is
really a generic LSR problem. I just didn't feel like fighting with LSR
and dealing with all the various targets swinging slightly in hard to
reason about ways. This problem is more pronounced on RISCV than any
other target due to our lack of addressing modes.

This change is not hugely important on it's own, but I have an upcoming
change to add support fo shNadd in LSR which biases us fairly strongly
towards adding more "base adds". Without this change, we see net
regression due to the increase in register pressure which is not
accounted for.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications