[all-commits] [llvm/llvm-project] c8dc6b: [SDAG] Improve `SimplifyDemandedBits` for mul (#90...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c8dc6b59d68635f73d2970b7fc8bc9c6c2684098
      https://github.com/llvm/llvm-project/commit/c8dc6b59d68635f73d2970b7fc8bc9c6c2684098
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-05-22 (Wed, 22 May 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll
    M llvm/test/CodeGen/X86/combine-srem.ll
    M llvm/test/CodeGen/X86/pmul.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll

  Log Message:
  -----------
  [SDAG] Improve `SimplifyDemandedBits` for mul (#90034)

If the RHS is a constant with X trailing zeros, then the X MSBs of the
LHS are not demanded.

Alive2: https://alive2.llvm.org/ce/z/F5CyJW
Fixes https://github.com/llvm/llvm-project/issues/56645.



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