[all-commits] [llvm/llvm-project] 267de8: [llvm-mca][AArch64] Add AArch64 version of clearsS...

[Rin Dobrescu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 267de8543c8671baa7e12c4d181e6c4e6e2342cd
      https://github.com/llvm/llvm-project/commit/267de8543c8671baa7e12c4d181e6c4e6e2342cd
  Author: Rin Dobrescu <irina.dobrescu at arm.com>
  Date:   2024-05-22 (Wed, 22 May 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
    A llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
    A llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s

  Log Message:
  -----------
  [llvm-mca][AArch64] Add AArch64 version of clearsSuperRegisters. (#92548)

This patch overrides the clearsSuperRegisters method defined in
MCInstrAnalysis to identify register writes that clear the upper portion
of all super-registers on AArch64 architecture.

On AArch64, a write to a general-purpose register of 32-bit data size is
defined to use the lower 32-bits of the register and zero extend the
upper 32-bits.
Similarly, SIMD and FP instructions operating on scalar data only access
the lower bits of the SIMD&FP register. The unused upper bits are
cleared to zero on a write.
This also applies to SIMD vector registers when the element size in bits
multiplied by the number of lanes is lower than 128. The upper 64 bits
of the vector register are cleared to zero on a write.



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