[all-commits] [llvm/llvm-project] cf1283: [SDAG] Don't treat ISD::SHL as a uniform binary op...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf128305bdada3ffb34054813a855d80b3948025
      https://github.com/llvm/llvm-project/commit/cf128305bdada3ffb34054813a855d80b3948025
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-05-22 (Wed, 22 May 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/bitfield-insert.ll
    M llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
    A llvm/test/CodeGen/X86/pr92720.ll

  Log Message:
  -----------
  [SDAG] Don't treat ISD::SHL as a uniform binary operator in `ShrinkDemandedOp` (#92753)

In `TargetLowering::ShrinkDemandedOp`, types of lhs and rhs may differ
before legalization.
In the original case, `VT` is `i64` and `SmallVT` is `i32`, but the type
of rhs is `i8`. Then invalid truncate nodes will be created.

See the description of ISD::SHL for further information:
> After legalization, the type of the shift amount is known to be
TLI.getShiftAmountTy(). Before legalization, the shift amount can be any
type, but care must be taken to ensure it is large enough.


https://github.com/llvm/llvm-project/blob/605ae4e93be8976095c7eedf5c08bfdb9ff71257/llvm/include/llvm/CodeGen/ISDOpcodes.h#L691-L712

This patch stops handling ISD::SHL in `TargetLowering::ShrinkDemandedOp`
and duplicates the logic in `TargetLowering::SimplifyDemandedBits`.
Additionally, it adds some additional checks like
`isNarrowingProfitable` and `isTypeDesirableForOp` to improve the
codegen on AArch64.

Fixes https://github.com/llvm/llvm-project/issues/92720.



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