[all-commits] [llvm/llvm-project] 675e7b: [RISCV] Support postRA vsetvl insertion pass (#70549)

Piyou Chen via All-commits all-commits at lists.llvm.org
Mon May 20 23:43:17 PDT 2024 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 675e7bd1b94f78f0567b4327f187841c0cde36f9
      https://github.com/llvm/llvm-project/commit/675e7bd1b94f78f0567b4327f187841c0cde36f9
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2024-05-21 (Tue, 21 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
    M llvm/test/CodeGen/RISCV/pr69586.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-store-extract-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
    M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Support postRA vsetvl insertion pass (#70549)

This patch try to get rid of vsetvl implict vl/vtype def-use chain and
improve the register allocation quality by moving the vsetvl insertion
pass after RVV register allocation

It will gain the benefit for the following optimization from

1. unblock scheduler's constraints by removing vl/vtype def-use chain
2. Support RVV re-materialization
3. Support partial spill

This patch add a new option `-riscv-vsetvl-after-rvv-regalloc=<1|0>` to
control this feature and default set as disable.



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