[all-commits] [llvm/llvm-project] 6246b4: [RISCV] Select ISD::AVGCEILS/AVGFLOORS as vaadd. (...
Craig Topper via All-commits
all-commits at lists.llvm.org
Mon May 20 23:24:43 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 6246b495adcbdff7d2ec4f37dfb656542adf909d
https://github.com/llvm/llvm-project/commit/6246b495adcbdff7d2ec4f37dfb656542adf909d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-05-20 (Mon, 20 May 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
Log Message:
-----------
[RISCV] Select ISD::AVGCEILS/AVGFLOORS as vaadd. (#92839)
I think the behaviors are the same if this describes their behavior.
AVGFLOORS sign extends the inputs by 1 bit, adds them, then does an
arithmetic shift right by 1 before truncating to the original bit width.
This is vaadd with rdn rounding mode.
AVGCEILS sign extends the inputs by 1 bit, adds them, then does an
arithmetic shift right by 1. If the bit shifted out is 1, it adds 1 to
the shifted value. Then truncates to the original bit width. This is vaadd
with rnu rounding mode.
I think this wasn't implemented previously because there was some
confusion about what average means. Some may expect average to round
towards zero, but there is no way to do that in RISC-V or with the
SelectionDAG nodes. Related issue
https://github.com/riscv/riscv-v-spec/issues/935
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