[all-commits] [llvm/llvm-project] fdd245: [MLIR][Vector] Implement transferXXPermutationLowe...

[Hugo Trachino via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fdd245ad856f85019bb408ed5c14984823e7077f
      https://github.com/llvm/llvm-project/commit/fdd245ad856f85019bb408ed5c14984823e7077f
  Author: Hugo Trachino <hugo.trachino at huawei.com>
  Date:   2024-05-20 (Mon, 20 May 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/Utils/VectorUtils.h
    M mlir/lib/Dialect/Vector/Transforms/LowerVectorTransfer.cpp
    M mlir/test/Dialect/Vector/vector-transfer-permutation-lowering.mlir

  Log Message:
  -----------
  [MLIR][Vector] Implement transferXXPermutationLowering as MaskableOpRewritePattern (#91987)

* Implements `TransferWritePermutationLowering`,
`TransferReadPermutationLowering` and
`TransferWriteNonPermutationLowering` as a MaskableOpRewritePattern.
Allowing to exit gracefully when such use of a xferOp is inside a
`vector::MaskOp`
* Updates MaskableOpRewritePattern to handle MemRefs and buffer
semantics providing empty `Value()` as a return value for
`matchAndRewriteMaskableOp` now represents successful rewriting without
value to replace the original op.

Split of https://github.com/llvm/llvm-project/pull/90835



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