[all-commits] [llvm/llvm-project] a7cd0c: [RISCV] Add a unaligned-scalar-mem feature like we...

[Craig Topper via All-commits]

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: a7cd0c61123889a632ceea67dc8c8e2c8753ae08
      https://github.com/llvm/llvm-project/commit/a7cd0c61123889a632ceea67dc8c8e2c8753ae08
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-05-17 (Fri, 17 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/pr56110.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll

  Log Message:
  -----------
  [RISCV] Add a unaligned-scalar-mem feature like we had in clang 17.

This is ORed with the fast-unaligned-access feature which applies
to scalar and vector together.:



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications