[all-commits] [llvm/llvm-project] c4bac7: [LLVM][AArch64]Use load/store with consecutive reg...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c4bac7f7dcd931a5e561604e95656a24c3d1c9d9
      https://github.com/llvm/llvm-project/commit/c4bac7f7dcd931a5e561604e95656a24c3d1c9d9
  Author: CarolineConcatto <caroline.concatto at arm.com>
  Date:   2024-05-17 (Fri, 17 May 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
    A llvm/test/CodeGen/AArch64/sve-callee-save-restore-pairs.ll

  Log Message:
  -----------
  [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (#77665)

…VE2.1 for spill/fill

When possible the spill/fill register in Frame Lowering uses the ld/st
consecutive pairs available in sme or sve2.1.



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