[all-commits] [llvm/llvm-project] d6f927: [X86] Use plain load/store instead of cmpxchg16b f...

[James Y Knight via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d6f9278ae9e587d2d23a9940a2364aaafba74735
      https://github.com/llvm/llvm-project/commit/d6f9278ae9e587d2d23a9940a2364aaafba74735
  Author: James Y Knight <jyknight at google.com>
  Date:   2024-05-16 (Thu, 16 May 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll
    M llvm/test/CodeGen/X86/atomic-non-integer.ll
    A llvm/test/CodeGen/X86/atomic-unaligned.ll
    M llvm/test/CodeGen/X86/atomic-unordered.ll
    M llvm/test/CodeGen/X86/atomic128.ll
    M llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll

  Log Message:
  -----------
  [X86] Use plain load/store instead of cmpxchg16b for atomics with AVX (#74275)

In late 2021, both Intel and AMD finally documented that every
AVX-capable CPU has always been guaranteed to execute aligned 16-byte
loads/stores atomically, and further, guaranteed that all future CPUs
with AVX will do so as well.

Therefore, we may use normal SSE 128-bit load/store instructions to
implement atomics, if AVX is enabled.

Per AMD64 Architecture Programmer's manual, 7.3.2 Access Atomicity:

> Processors that report [AVX] extend the atomicity for cacheable,
> naturally-aligned single loads or stores from a quadword to a double
> quadword.

Per Intel's SDM:

> Processors that enumerate support for Intel(R) AVX guarantee that the
> 16-byte memory operations performed by the following instructions will
> always be carried out atomically:
> - MOVAPD, MOVAPS, and MOVDQA.
> - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128.
> - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded with
>   EVEX.128 and k0 (masking disabled).

This was also confirmed to be true for Zhaoxin CPUs with AVX, in
https://gcc.gnu.org/PR104688



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